src/drivers/intel/fsp2_0/save_mrc_data.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <bootstate.h>
   5 #include <cbmem.h>
   6 #include <console/console.h>
   7 #include <fsp/util.h>
   8 #include <mrc_cache.h>
   9
  10 static void save_mrc_data(void *unused)
  11 {
  12         size_t mrc_data_size;
  13         const void *mrc_data;
  14         uint32_t *fspm_version;
  15
  16         if (acpi_is_wakeup_s3())
  17                 return;
  18
  19         fspm_version = cbmem_find(CBMEM_ID_FSPM_VERSION);
  20         if (!fspm_version) {
  21                 printk(BIOS_ERR, "Failed to read FSP-M version from cbmem.\n");
  22                 return;
  23         }
  24
  25         mrc_data = fsp_find_nv_storage_data(&mrc_data_size);
  26         if (!mrc_data) {
  27                 printk(BIOS_ERR, "FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
  28                 return;
  29         }
  30
  31         /*
  32          * Save MRC data to SPI flash. By always saving the data this forces
  33          * a retrain after a trip through ChromeOS recovery path. The
  34          * code which saves the data to flash doesn't write if the latest
  35          * training data matches this one.
  36          */
  37         if (mrc_cache_stash_data(MRC_TRAINING_DATA, *fspm_version, mrc_data,
  38                                  mrc_data_size) < 0)
  39                 printk(BIOS_ERR, "Failed to stash MRC data\n");
  40 }
  41
  42 /*
  43  * Should be done before ramstage_cse_fw_sync() to avoid traning memory twice on
  44  * a cold boot after a full firmware update.
  45  */
  46 #if CONFIG(SAVE_MRC_AFTER_FSPS)
  47 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, save_mrc_data, NULL);
  48 #else
  49 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, save_mrc_data, NULL);
  50 #endif