src/drivers/intel/fsp2_0/silicon_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <arch/null_breakpoint.h>
   4 #include <bootsplash.h>
   5 #include <cbfs.h>
   6 #include <cbmem.h>
   7 #include <commonlib/fsp.h>
   8 #include <commonlib/stdlib.h>
   9 #include <console/console.h>
  10 #include <fsp/api.h>
  11 #include <fsp/util.h>
  12 #include <program_loading.h>
  13 #include <soc/intel/common/vbt.h>
  14 #include <stage_cache.h>
  15 #include <string.h>
  16 #include <timestamp.h>
  17 #include <types.h>
  18 #include <mode_switch.h>
  19
  20 struct fsp_header fsps_hdr;
  21
  22 struct fsp_multi_phase_get_number_of_phases_params {
  23         uint32_t number_of_phases;
  24         uint32_t phases_executed;
  25 };
  26
  27 /* Callbacks for SoC/Mainboard specific overrides */
  28 void __weak platform_fsp_multi_phase_init_cb(uint32_t phase_index)
  29 {
  30         /* Leave for the SoC/Mainboard to implement if necessary. */
  31 }
  32
  33 /* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2
  34  * has multiple stages as below.
  35  */
  36 enum fsp_silicon_init_phases {
  37         FSP_SILICON_INIT_API,
  38         FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API,
  39         FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API
  40 };
  41
  42 static void fsps_return_value_handler(enum fsp_silicon_init_phases phases, uint32_t status)
  43 {
  44         uint8_t postcode;
  45
  46         /* Handle any reset request returned by FSP-S APIs */
  47         fsp_handle_reset(status);
  48
  49         if (status == FSP_SUCCESS)
  50                 return;
  51         /* Handle all other errors returned by FSP-S APIs */
  52         /* Assume video failure if attempted to initialize graphics */
  53         if (CONFIG(RUN_FSP_GOP) && vbt_get())
  54                 postcode = POST_VIDEO_FAILURE;
  55         else
  56                 postcode = POST_HW_INIT_FAILURE; /* else generic */
  57
  58         switch (phases) {
  59         case FSP_SILICON_INIT_API:
  60                 die_with_post_code(postcode, "FspSiliconInit returned with error 0x%08x\n",
  61                                 status);
  62                 break;
  63         case FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API:
  64                 printk(BIOS_SPEW, "FspMultiPhaseSiInit NumberOfPhases returned 0x%08x\n",
  65                                 status);
  66                 break;
  67         case FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API:
  68                 printk(BIOS_SPEW, "FspMultiPhaseSiInit ExecutePhase returned 0x%08x\n",
  69                                 status);
  70                 break;
  71         default:
  72                 break;
  73         }
  74 }
  75
  76 bool fsp_is_multi_phase_init_enabled(void)
  77 {
  78         return CONFIG(FSPS_USE_MULTI_PHASE_INIT) &&
  79                          (fsps_hdr.fsp_multi_phase_si_init_entry_offset != 0);
  80 }
  81
  82 static void fsp_fill_common_arch_params(FSPS_UPD *supd)
  83 {
  84 #if CONFIG(FSPS_HAS_ARCH_UPD)
  85         FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
  86         s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled();
  87 #endif
  88 }
  89
  90 static void do_silicon_init(struct fsp_header *hdr)
  91 {
  92         FSPS_UPD *upd, *supd;
  93         fsp_silicon_init_fn silicon_init;
  94         uint32_t status;
  95         fsp_multi_phase_si_init_fn multi_phase_si_init;
  96         struct fsp_multi_phase_params multi_phase_params;
  97         struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
  98
  99         supd = (FSPS_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
 100
 101         fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE);
 102
 103         /* FSPS UPD and coreboot structure sizes should match. However, enforcing the exact
 104          * match mandates simultaneous updates to coreboot and FSP repos. Allow coreboot
 105          * to proceed if its UPD structure is smaller than FSP one to enable staggered UPD
 106          * update process on both sides. The mismatch indicates a temporary build problem,
 107          * don't leave it like this as FSP default settings can be bad choices for coreboot.
 108          */
 109         if (!hdr->cfg_region_size || hdr->cfg_region_size < sizeof(FSPS_UPD))
 110                 die_with_post_code(POST_INVALID_VENDOR_BINARY,
 111                         "Invalid FSPS UPD region\n");
 112         else if (hdr->cfg_region_size > sizeof(FSPS_UPD))
 113                 printk(BIOS_ERR, "FSP and coreboot are out of sync! FSPS UPD size > coreboot\n");
 114
 115         upd = xmalloc(hdr->cfg_region_size);
 116
 117         memcpy(upd, supd, hdr->cfg_region_size);
 118
 119         /* Fill common settings on behalf of chipset. */
 120         if (CONFIG(FSPS_HAS_ARCH_UPD))
 121                 fsp_fill_common_arch_params(upd);
 122         /* Give SoC/mainboard a chance to populate entries */
 123         platform_fsp_silicon_init_params_cb(upd);
 124
 125         /* Populate logo related entries */
 126         if (CONFIG(BMP_LOGO))
 127                 soc_load_logo(upd);
 128
 129         /* Call SiliconInit */
 130         silicon_init = (void *)(uintptr_t)(hdr->image_base +
 131                                  hdr->fsp_silicon_init_entry_offset);
 132         fsp_debug_before_silicon_init(silicon_init, supd, upd);
 133
 134         timestamp_add_now(TS_FSP_SILICON_INIT_START);
 135         post_code(POST_FSP_SILICON_INIT);
 136
 137         /* FSP disables the interrupt handler so remove debug exceptions temporarily  */
 138         null_breakpoint_disable();
 139         if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
 140                 status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd);
 141         else
 142                 status = silicon_init(upd);
 143         null_breakpoint_init();
 144
 145         printk(BIOS_INFO, "FSPS returned %x\n", status);
 146
 147         timestamp_add_now(TS_FSP_SILICON_INIT_END);
 148         post_code(POST_FSP_SILICON_EXIT);
 149
 150         if (CONFIG(BMP_LOGO))
 151                 bmp_release_logo();
 152
 153         fsp_debug_after_silicon_init(status);
 154         fsps_return_value_handler(FSP_SILICON_INIT_API, status);
 155
 156         /* Reinitialize CPUs if FSP-S has done MP Init */
 157         if (CONFIG(USE_INTEL_FSP_MP_INIT))
 158                 do_mpinit_after_fsp();
 159
 160         if (!CONFIG(PLATFORM_USES_FSP2_2))
 161                 return;
 162
 163         /* Check if SoC user would like to call Multi Phase Init */
 164         if (!fsp_is_multi_phase_init_enabled())
 165                 return;
 166
 167         /* Call MultiPhaseSiInit */
 168         multi_phase_si_init = (void *)(uintptr_t)(hdr->image_base +
 169                          hdr->fsp_multi_phase_si_init_entry_offset);
 170
 171         /* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */
 172         if (multi_phase_si_init == NULL)
 173                 return;
 174
 175         post_code(POST_FSP_MULTI_PHASE_SI_INIT_ENTRY);
 176         timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_START);
 177         /* Get NumberOfPhases Value */
 178         multi_phase_params.multi_phase_action = GET_NUMBER_OF_PHASES;
 179         multi_phase_params.phase_index = 0;
 180         multi_phase_params.multi_phase_param_ptr = &multi_phase_get_number;
 181         status = multi_phase_si_init(&multi_phase_params);
 182         fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_GET_NUMBER_OF_PHASES_API, status);
 183
 184         /* Execute Multi Phase Execution */
 185         for (uint32_t i = 1; i <= multi_phase_get_number.number_of_phases; i++) {
 186                 printk(BIOS_SPEW, "Executing Phase %u of FspMultiPhaseSiInit\n", i);
 187                 /*
 188                  * Give SoC/mainboard a chance to perform any operation before
 189                  * Multi Phase Execution
 190                  */
 191                 platform_fsp_multi_phase_init_cb(i);
 192
 193                 multi_phase_params.multi_phase_action = EXECUTE_PHASE;
 194                 multi_phase_params.phase_index = i;
 195                 multi_phase_params.multi_phase_param_ptr = NULL;
 196                 status = multi_phase_si_init(&multi_phase_params);
 197                 fsps_return_value_handler(FSP_MULTI_PHASE_SI_INIT_EXECUTE_PHASE_API, status);
 198         }
 199         timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
 200         post_code(POST_FSP_MULTI_PHASE_SI_INIT_EXIT);
 201 }
 202
 203 static void *fsps_allocator(void *arg_unused, size_t size, const union cbfs_mdata *mdata_unused)
 204 {
 205         return cbmem_add(CBMEM_ID_REFCODE, size);
 206 }
 207
 208 void fsps_load(void)
 209 {
 210         struct fsp_load_descriptor fspld = {
 211                 .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS),
 212                 .alloc = fsps_allocator,
 213         };
 214         struct prog *fsps = &fspld.fsp_prog;
 215         static int load_done;
 216
 217         if (load_done)
 218                 return;
 219
 220         timestamp_add_now(TS_FSP_SILICON_INIT_LOAD);
 221
 222         if (resume_from_stage_cache()) {
 223                 printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n");
 224                 stage_cache_load_stage(STAGE_REFCODE, fsps);
 225                 if (fsp_validate_component(&fsps_hdr, prog_start(fsps), prog_size(fsps)))
 226                         die("On resume fsps header is invalid\n");
 227                 load_done = 1;
 228                 return;
 229         }
 230
 231         if (fsp_load_component(&fspld, &fsps_hdr) != CB_SUCCESS)
 232                 die("FSP-S failed to load\n");
 233
 234         stage_cache_add(STAGE_REFCODE, fsps);
 235
 236         load_done = 1;
 237 }
 238
 239 void preload_fsps(void)
 240 {
 241         if (!CONFIG(CBFS_PRELOAD))
 242                 return;
 243
 244         printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_S_CBFS);
 245         cbfs_preload(CONFIG_FSP_S_CBFS);
 246 }
 247
 248 void fsp_silicon_init(void)
 249 {
 250         fsps_load();
 251         do_silicon_init(&fsps_hdr);
 252
 253         if (CONFIG(DISPLAY_FSP_TIMESTAMPS))
 254                 fsp_display_timestamp();
 255 }
 256
 257 __weak void soc_load_logo(FSPS_UPD *supd) { }