src/mainboard/system76/kbl-u/devicetree.cb

   1 chip soc/intel/skylake
   2         # Send an extra VR mailbox command for the PS4 exit issue
   3         register "SendVrMbxCmd" = "2"
   4
   5         # Power limit
   6         register "power_limits_config" = "{
   7                 .tdp_pl1_override = 20,
   8                 .tdp_pl2_override = 30,
   9         }"
  10
  11         # Enable Enhanced Intel SpeedStep
  12         register "eist_enable" = "1"
  13
  14         # Serial I/O
  15         register "SerialIoDevMode" = "{
  16                 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
  17         }"
  18
  19         # Serial IRQ
  20         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  21
  22         # Power
  23         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  24         register "PmConfigSlpS4MinAssert" = "1"         # 1s
  25         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
  26         register "PmConfigSlpAMinAssert" = "3"          # 2s
  27
  28         # FSP Configuration
  29         register "SkipExtGfxScan" = "1"
  30         register "SaGv" = "SaGv_Enabled"
  31
  32         # VR Settings Configuration for 4 Domains
  33         #+----------------+-----------+-----------+-------------+----------+
  34         #| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
  35         #+----------------+-----------+-----------+-------------+----------+
  36         #| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
  37         #| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
  38         #| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
  39         #| Psi3Enable     | 1         | 1         | 1           | 1        |
  40         #| Psi4Enable     | 1         | 1         | 1           | 1        |
  41         #| ImonSlope      | 0         | 0         | 0           | 0        |
  42         #| ImonOffset     | 0         | 0         | 0           | 0        |
  43         #| IccMax         | 5A        | 64A       | 31A         | 31A      |
  44         #| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
  45         #+----------------+-----------+-----------+-------------+----------+
  46         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  47                 .vr_config_enable = 1,
  48                 .psi1threshold = VR_CFG_AMP(20),
  49                 .psi2threshold = VR_CFG_AMP(4),
  50                 .psi3threshold = VR_CFG_AMP(1),
  51                 .psi3enable = 0,
  52                 .psi4enable = 0,
  53                 .imon_slope = 0x0,
  54                 .imon_offset = 0x0,
  55                 .icc_max = VR_CFG_AMP(5),
  56                 .voltage_limit = 1520,
  57                 .ac_loadline = 1030,
  58                 .dc_loadline = 1030,
  59         }"
  60
  61         register "domain_vr_config[VR_IA_CORE]" = "{
  62                 .vr_config_enable = 1,
  63                 .psi1threshold = VR_CFG_AMP(20),
  64                 .psi2threshold = VR_CFG_AMP(5),
  65                 .psi3threshold = VR_CFG_AMP(1),
  66                 .psi3enable = 0,
  67                 .psi4enable = 0,
  68                 .imon_slope = 0x0,
  69                 .imon_offset = 0x0,
  70                 .icc_max = VR_CFG_AMP(64),
  71                 .voltage_limit = 1520,
  72                 .ac_loadline = 240,
  73                 .dc_loadline = 240,
  74         }"
  75
  76         register "domain_vr_config[VR_GT_UNSLICED]" = "{
  77                 .vr_config_enable = 1,
  78                 .psi1threshold = VR_CFG_AMP(20),
  79                 .psi2threshold = VR_CFG_AMP(5),
  80                 .psi3threshold = VR_CFG_AMP(1),
  81                 .psi3enable = 0,
  82                 .psi4enable = 0,
  83                 .imon_slope = 0x0,
  84                 .imon_offset = 0x0,
  85                 .icc_max = VR_CFG_AMP(31),
  86                 .voltage_limit = 1520,
  87                 .ac_loadline = 310,
  88                 .dc_loadline = 310,
  89         }"
  90
  91         register "domain_vr_config[VR_GT_SLICED]" = "{
  92                 .vr_config_enable = 1,
  93                 .psi1threshold = VR_CFG_AMP(20),
  94                 .psi2threshold = VR_CFG_AMP(5),
  95                 .psi3threshold = VR_CFG_AMP(1),
  96                 .psi3enable = 0,
  97                 .psi4enable = 0,
  98                 .imon_slope = 0x0,
  99                 .imon_offset = 0x0,
 100                 .icc_max = VR_CFG_AMP(31),
 101                 .voltage_limit = 1520,
 102                 .ac_loadline = 310,
 103                 .dc_loadline = 310,
 104         }"
 105
 106         device cpu_cluster 0 on end
 107
 108         device domain 0 on
 109                 device ref system_agent on end
 110                 device ref igpu on end
 111                 device ref sa_thermal on end
 112                 device ref south_xhci on
 113                         # USB2
 114                         register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"         # Type-A port right
 115                         register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"        # 3G / LTE
 116                         register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"      # Type-C port right
 117                         register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"        # Camera
 118                         register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)"        # Bluetooth
 119                         register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"        # Type-A port left
 120                         register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"      # Type-C port right
 121                         # USB3
 122                         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"     # Type-A port right
 123                         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"     # 4G
 124                         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"     # Type C port right
 125                         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"     # Type-A port left
 126                 end
 127                 device ref thermal on end
 128                 device ref sata on
 129                         register "SataSalpSupport" = "0"
 130                         register "SataPortsEnable[0]" = "1"
 131                         register "SataPortsEnable[2]" = "1"
 132                         register "SataSpeedLimit" = "2"
 133                 end
 134                 device ref pcie_rp1 on
 135                         # Root port #1 x4 (TBT)
 136                         register "PcieRpEnable[0]" = "1"
 137                         register "PcieRpClkReqSupport[0]" = "1"
 138                         register "PcieRpClkReqNumber[0]" = "4"
 139                         register "PcieRpClkSrcNumber[0]" = "4"
 140                         register "PcieRpAdvancedErrorReporting[0]" = "1"
 141                         register "PcieRpLtrEnable[0]" = "1"
 142                         register "PcieRpHotPlug[0]" = "1"
 143                 end
 144                 device ref pcie_rp5 on
 145                         # Root port #5 x1 (LAN)
 146                         register "PcieRpEnable[4]" = "1"
 147                         register "PcieRpClkReqSupport[4]" = "1"
 148                         register "PcieRpClkReqNumber[4]" = "3"
 149                         register "PcieRpClkSrcNumber[4]" = "3"
 150                         register "PcieRpAdvancedErrorReporting[4]" = "1"
 151                         register "PcieRpLtrEnable[4]" = "1"
 152                 end
 153                 device ref pcie_rp6 on
 154                         # Root port #6 x1 (WLAN)
 155                         register "PcieRpEnable[5]" = "1"
 156                         register "PcieRpClkReqSupport[5]" = "1"
 157                         register "PcieRpClkReqNumber[5]" = "2"
 158                         register "PcieRpClkSrcNumber[5]" = "2"
 159                         register "PcieRpAdvancedErrorReporting[5]" = "1"
 160                         register "PcieRpLtrEnable[5]" = "1"
 161                 end
 162                 device ref pcie_rp9 on
 163                         # Root port #9 x4 (NVMe)
 164                         register "PcieRpEnable[8]" = "1"
 165                         register "PcieRpClkReqSupport[8]" = "1"
 166                         register "PcieRpClkReqNumber[8]" = "5"
 167                         register "PcieRpClkSrcNumber[8]" = "5"
 168                         register "PcieRpAdvancedErrorReporting[8]" = "1"
 169                         register "PcieRpLtrEnable[8]" = "1"
 170                 end
 171                 device ref lpc_espi on
 172                         register "gen1_dec" = "0x000c0681"
 173                         register "gen2_dec" = "0x000c1641"
 174                         register "gen3_dec" = "0x00040069"
 175                         chip drivers/pc80/tpm
 176                                 device pnp 0c31.0 on end
 177                         end
 178                 end
 179                 device ref p2sb off end
 180                 device ref pmc on
 181                         register "gpe0_dw0" = "GPP_C"
 182                         register "gpe0_dw1" = "GPP_D"
 183                         register "gpe0_dw2" = "GPP_E"
 184                 end
 185                 device ref hda on end
 186                 device ref smbus on end
 187                 device ref fast_spi on end
 188         end
 189 end