src/mainboard/system76/tgl-u/variants/lemp10/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <mainboard/gpio.h>
   4 #include <soc/gpio.h>
   5
   6 static const struct pad_config gpio_table[] = {
   7         PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
   8         PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
   9         PAD_CFG_GPI(GPD2, NONE, PWROK),
  10         PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
  11         PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
  12         PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
  13         PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // SLP_A# - test point
  14         PAD_CFG_GPO(GPD7, 1, PWROK), // GPD7_REST
  15         PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
  16         PAD_CFG_GPO(GPD9, 0, PWROK), // GPD9_RTD3
  17         PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), // SLP_S5# - test point
  18         PAD_CFG_GPI(GPD11, UP_20K, DEEP),
  19
  20         PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO_0
  21         PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO_1
  22         PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO_2
  23         PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO_3
  24         PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_N
  25         PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK
  26         PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N
  27         PAD_NC(GPP_A7, NONE),
  28         PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), // CNVI_RST#
  29         PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), // CNVI_CLKREQ
  30         PAD_NC(GPP_A10, NONE), // GPPC_DMIC_DATA
  31         PAD_NC(GPP_A11, NONE),
  32         PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), // SATAGP1
  33         PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
  34         PAD_NC(GPP_A14, NONE), // GPPC_DMIC_CLK
  35         PAD_NC(GPP_A15, NONE), // USB_OC2#
  36         PAD_NC(GPP_A16, NONE), // USB_OC3#
  37         PAD_NC(GPP_A17, NONE),
  38         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
  39         PAD_NC(GPP_A19, NONE),
  40         PAD_NC(GPP_A20, NONE),
  41         PAD_NC(GPP_A21, NONE),
  42         PAD_NC(GPP_A22, NONE),
  43         PAD_CFG_GPO(GPP_A23, 0, PLTRST), // TC_RETIMER_FORCE_PWR
  44
  45         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
  46         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
  47         PAD_CFG_GPI(GPP_B2, UP_20K, DEEP), // VRALERT#
  48         PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), // GPP_B3 - touchpad interrupt
  49         PAD_NC(GPP_B4, NONE),
  50         PAD_NC(GPP_B5, NONE), // PCH_FLASH_I2C_SDA - test point
  51         PAD_NC(GPP_B6, NONE), // PCH_FLASH_I2C_SCL - test point
  52         PAD_NC(GPP_B7, NONE),
  53         PAD_NC(GPP_B8, NONE),
  54         PAD_NC(GPP_B9, NONE),
  55         PAD_NC(GPP_B10, NONE),
  56         PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA_I2C_INT
  57         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
  58         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
  59         PAD_CFG_GPO(GPP_B14, 0, DEEP), // PCH_SPKR
  60         PAD_NC(GPP_B15, NONE),
  61         PAD_NC(GPP_B16, NONE), // PCH_GPP_B16 - test point
  62         PAD_NC(GPP_B17, NONE),
  63         PAD_NC(GPP_B18, NONE), // PCH_GPP_B18 - No reboot strap
  64         PAD_NC(GPP_B19, NONE),
  65         PAD_NC(GPP_B20, NONE),
  66         PAD_NC(GPP_B21, NONE),
  67         PAD_NC(GPP_B22, NONE),
  68         PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23
  69
  70         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
  71         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
  72         PAD_CFG_GPO(GPP_C2, 1, DEEP), // PCH_GPP_C2 - ME TLS strap
  73         PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
  74         PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
  75         PAD_NC(GPP_C5, NONE), // PCH_GPP_C5 - boot strap bit 0
  76         PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1), // TBT_I2C_SCL
  77         PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1), // TBT_I2C_SDA
  78         PAD_NC(GPP_C8, NONE),
  79         _PAD_CFG_STRUCT(GPP_C9, 0x40100100, 0x3000), // TPM_PIRQ#
  80         PAD_NC(GPP_C10, NONE),
  81         PAD_NC(GPP_C11, NONE),
  82         PAD_NC(GPP_C12, NONE),
  83         PAD_CFG_GPO(GPP_C13, 1, PLTRST), // SSD1_PWR_DN#
  84         PAD_NC(GPP_C14, DN_20K),
  85         PAD_NC(GPP_C15, NONE),
  86         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // T_SDA
  87         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // T_SCL
  88         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA
  89         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL
  90         PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD
  91         PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD
  92         PAD_CFG_GPO(GPP_C22, 1, PLTRST), // GPP_C12_RTD3
  93         _PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000), // PCH_GPP_C23
  94
  95         PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
  96         PAD_CFG_GPI(GPP_D1, NONE, DEEP), // DDR_TYPE_D1
  97         PAD_CFG_GPI(GPP_D2, DN_20K, DEEP), // LEDKB_DET#
  98         PAD_CFG_GPI(GPP_D3, DN_20K, DEEP), // BOARD_ID
  99         PAD_NC(GPP_D4, NONE),
 100         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD1_CLKREQ#
 101         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // WLAN_CLKREQ#
 102         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // CARD_CLKREQ#
 103         PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // SSD2_CLKREQ#
 104         PAD_CFG_GPO(GPP_D9, 1, PLTRST), // GPP_D13_RTD3 - schematics name incorrect
 105         PAD_NC(GPP_D10, NONE), // GPP_D10 - I2C / TBT_LSX2 pin voltage (L=1.8V, H=3.3V)
 106         PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
 107         PAD_NC(GPP_D12, NONE), // GPP_D12 - I2C / TBT_LSX3 pin voltage (L=1.8V, H=3.3V)
 108         PAD_NC(GPP_D13, NONE),
 109         PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_DN#
 110         PAD_NC(GPP_D15, NONE),
 111         PAD_NC(GPP_D16, NONE),
 112         PAD_CFG_GPI(GPP_D17, NONE, DEEP), // DDR_TYPE_D17
 113         PAD_CFG_GPI(GPP_D18, NONE, DEEP), // DDR_TYPE_D18
 114         PAD_NC(GPP_D19, NONE),
 115
 116         PAD_NC(GPP_E0, NONE),
 117         PAD_CFG_GPO(GPP_E1, 0, PLTRST), // ROM_I2C_EN
 118         PAD_NC(GPP_E2, NONE),
 119         PAD_CFG_GPI(GPP_E3, DN_20K, DEEP), // SB_KBCRST#
 120         PAD_NC(GPP_E4, NONE), // DEVSLP0
 121         PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // DEVSLP1
 122         PAD_NC(GPP_E6, NONE), // PCH_GPP_E6 - reserved strap
 123         PAD_NC(GPP_E7, NONE),
 124         PAD_NC(GPP_E8, NONE),
 125         PAD_NC(GPP_E9, NONE), // USB_OC0#
 126         PAD_NC(GPP_E10, NONE), // PCH_GPP_E10 - THC0_SPI1 chip select
 127         PAD_NC(GPP_E11, NONE), // PCH_GPP_E11 - THC0_SPI1 clock
 128         PAD_NC(GPP_E12, NONE),
 129         PAD_NC(GPP_E13, NONE),
 130         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
 131         PAD_CFG_GPI(GPP_E15, DN_20K, DEEP), // SCI#
 132         _PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000), // SMI#
 133         PAD_NC(GPP_E17, NONE),
 134         // GPP_E18 (TBT_LSX0_TXD) configured by FSP (Ref: Intel doc 617016)
 135         // GPP_E19 (TBT_LSX0_RXD) configured by FSP (Ref: Intel doc 617016)
 136         _PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000), // SWI#
 137         PAD_NC(GPP_E21, NONE), // GPP_E21 - DDP2 I2C / TBT_LSX1 pin voltage (L=1.8V, H=3.3V)
 138         PAD_NC(GPP_E22, NONE),
 139         PAD_NC(GPP_E23, NONE),
 140
 141         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
 142         PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
 143         PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
 144         PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
 145         PAD_NC(GPP_F4, NONE),
 146         PAD_NC(GPP_F5, NONE),
 147         PAD_NC(GPP_F6, NONE), // CNVI_GNSS_PA_BLANKING
 148         PAD_NC(GPP_F7, NONE), // GPP_F7 - reserved strap
 149         PAD_NC(GPP_F8, NONE),
 150         PAD_NC(GPP_F9, NONE),
 151         PAD_NC(GPP_F10, NONE), // GPP_F10 - reserved strap
 152         PAD_NC(GPP_F11, NONE),
 153         PAD_NC(GPP_F12, NONE),
 154         PAD_NC(GPP_F13, NONE),
 155         PAD_NC(GPP_F14, NONE),
 156         PAD_NC(GPP_F15, NONE),
 157         PAD_NC(GPP_F16, NONE),
 158         PAD_CFG_GPI(GPP_F17, NONE, PLTRST), // TPM_DET#
 159         PAD_NC(GPP_F18, NONE),
 160         PAD_NC(GPP_F19, NONE),
 161         PAD_NC(GPP_F20, NONE), // EXT_PWR_GATE#
 162         PAD_CFG_GPI(GPP_F21, DN_20K, DEEP), // EXT_PWR_GATE2#
 163         PAD_NC(GPP_F22, NONE), // VNN_CTRL
 164         PAD_NC(GPP_F23, NONE), // V1P05_CTRL
 165
 166         PAD_NC(GPP_H0, DN_20K), // GPP_H0 - boot strap bit 1
 167         PAD_NC(GPP_H1, DN_20K), // GPP_H1 - boot strap bit 2
 168         PAD_NC(GPP_H2, DN_20K), // GPP_H2 - boot strap bit 3
 169         PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
 170         PAD_NC(GPP_H4, NONE),
 171         PAD_NC(GPP_H5, NONE),
 172         PAD_CFG_GPI(GPP_H6, NONE, DEEP), // test point
 173         PAD_NC(GPP_H7, NONE), // test point
 174         PAD_CFG_GPI(GPP_H8, DN_20K, DEEP), // CNVI_MFUART2_RXD
 175         PAD_CFG_GPI(GPP_H9, DN_20K, DEEP), // CNVI_MFUART2_TXD
 176         PAD_NC(GPP_H10, NONE),
 177         PAD_NC(GPP_H11, NONE),
 178         PAD_NC(GPP_H12, NONE),
 179         PAD_NC(GPP_H13, NONE),
 180         PAD_NC(GPP_H14, NONE), // G_INT1
 181         PAD_NC(GPP_H15, NONE),
 182         PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), // HDMI_CTRLCLK
 183         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
 184         PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
 185         PAD_NC(GPP_H19, NONE), // CNVI_WAKE#
 186         PAD_NC(GPP_H20, NONE), // PM_CLKRUN#
 187         PAD_NC(GPP_H21, NONE),
 188         PAD_NC(GPP_H22, NONE),
 189         PAD_NC(GPP_H23, NONE),
 190
 191         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
 192         PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
 193         PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
 194         PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
 195         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
 196         PAD_NC(GPP_R5, NONE),
 197         PAD_NC(GPP_R6, NONE),
 198         PAD_NC(GPP_R7, NONE),
 199
 200         PAD_NC(GPP_S0, NONE),
 201         PAD_NC(GPP_S1, NONE),
 202         PAD_NC(GPP_S2, NONE),
 203         PAD_NC(GPP_S3, NONE),
 204         PAD_NC(GPP_S4, NONE),
 205         PAD_NC(GPP_S5, NONE),
 206         PAD_CFG_GPI(GPP_S6, NONE, DEEP),
 207         PAD_CFG_GPI(GPP_S7, NONE, DEEP),
 208         PAD_NC(GPP_T2, NONE),
 209         PAD_NC(GPP_T3, NONE),
 210         PAD_NC(GPP_U4, NONE),
 211         PAD_NC(GPP_U5, NONE),
 212 };
 213
 214 void mainboard_configure_gpios(void)
 215 {
 216         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 217 }