soc/intel/elkhartlake: Make PCIe root port speed limit configurable
[coreboot.git] / configs / config.google_skyrim.with_binaries
blob530ace4eec53b2aead9c9117ba9c97b82994d37f
1 CONFIG_TIMESTAMPS_ON_CONSOLE=y
2 CONFIG_USE_AMD_BLOBS=y
3 CONFIG_VENDOR_GOOGLE=y
4 CONFIG_VGA_BIOS_ID="1002,1506"
5 CONFIG_AMD_FWM_POSITION_INDEX=3
6 CONFIG_VGA_BIOS=y
7 CONFIG_CONSOLE_POST=y
8 CONFIG_BOARD_GOOGLE_SKYRIM=y
9 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
10 CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin"
11 CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin"
12 CONFIG_FSP_M_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_M.fd"
13 CONFIG_FSP_S_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_S.fd"
14 CONFIG_ASYNC_FILE_LOADING=y
15 CONFIG_PSP_SOFTFUSE_BITS="34 28"
16 CONFIG_UART_PCI_ADDR=0x0
17 CONFIG_RUN_FSP_GOP=y
18 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
19 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
20 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
21 CONFIG_DISPLAY_HOBS=y
22 CONFIG_DISPLAY_UPD_DATA=y
23 CONFIG_ADD_FSP_BINARIES=y
24 CONFIG_POST_IO_PORT=0x80
25 CONFIG_PAYLOAD_NONE=y
26 CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
27 CONFIG_DISPLAY_FSP_HEADER=y
28 CONFIG_FATAL_ASSERTS=y
29 CONFIG_DEBUG_SMI=y
30 CONFIG_WRITE_STB_BUFFER_TO_CONSOLE=y
31 CONFIG_ADD_POSTCODES_TO_STB=y