soc/intel/*: Use SSDT to pass A4GB and A4GS
commit08769c6d1404c1be0333273d8b988544750ce87d
authorArthur Heymans <arthur@aheymans.xyz>
Mon, 9 May 2022 12:33:15 +0000 (9 14:33 +0200)
committerArthur Heymans <arthur@aheymans.xyz>
Mon, 16 May 2022 06:53:46 +0000 (16 06:53 +0000)
treeef37aeb920efea81b84ecf50c2ab990c09541b30
parent159520ed7881d1be2fdd02ee13040e8e21a9833c
soc/intel/*: Use SSDT to pass A4GB and A4GS

GNVS is more fragile as you need to keep struct elements in sync with
ASL code.

Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
25 files changed:
src/soc/intel/alderlake/acpi.c
src/soc/intel/alderlake/chip.c
src/soc/intel/apollolake/acpi.c
src/soc/intel/apollolake/acpi/globalnvs.asl
src/soc/intel/apollolake/acpi/northbridge.asl
src/soc/intel/apollolake/chip.c
src/soc/intel/apollolake/include/soc/nvs.h
src/soc/intel/cannonlake/acpi.c
src/soc/intel/cannonlake/chip.c
src/soc/intel/common/block/acpi/acpi/globalnvs.asl
src/soc/intel/common/block/acpi/acpi/northbridge.asl
src/soc/intel/common/block/include/intelblocks/nvs.h
src/soc/intel/common/block/include/intelblocks/systemagent.h
src/soc/intel/common/block/systemagent/systemagent.c
src/soc/intel/elkhartlake/acpi.c
src/soc/intel/elkhartlake/chip.c
src/soc/intel/icelake/acpi.c
src/soc/intel/icelake/chip.c
src/soc/intel/jasperlake/acpi.c
src/soc/intel/jasperlake/chip.c
src/soc/intel/skylake/acpi.c
src/soc/intel/skylake/acpi/systemagent.asl
src/soc/intel/skylake/chip.c
src/soc/intel/tigerlake/acpi.c
src/soc/intel/tigerlake/chip.c