src/soc/intel/tigerlake/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <acpi/acpi_gnvs.h>
   5 #include <acpi/acpigen.h>
   6 #include <device/mmio.h>
   7 #include <arch/smp/mpspec.h>
   8 #include <console/console.h>
   9 #include <device/device.h>
  10 #include <device/pci_ops.h>
  11 #include <intelblocks/cpulib.h>
  12 #include <intelblocks/pmclib.h>
  13 #include <intelblocks/acpi.h>
  14 #include <soc/cpu.h>
  15 #include <soc/iomap.h>
  16 #include <soc/nvs.h>
  17 #include <soc/pci_devs.h>
  18 #include <soc/pm.h>
  19 #include <soc/soc_chip.h>
  20 #include <soc/systemagent.h>
  21
  22 /*
  23  * List of supported C-states in this processor.
  24  */
  25 enum {
  26         C_STATE_C0,             /* 0 */
  27         C_STATE_C1,             /* 1 */
  28         C_STATE_C1E,            /* 2 */
  29         C_STATE_C6_SHORT_LAT,   /* 3 */
  30         C_STATE_C6_LONG_LAT,    /* 4 */
  31         C_STATE_C7_SHORT_LAT,   /* 5 */
  32         C_STATE_C7_LONG_LAT,    /* 6 */
  33         C_STATE_C7S_SHORT_LAT,  /* 7 */
  34         C_STATE_C7S_LONG_LAT,   /* 8 */
  35         C_STATE_C8,             /* 9 */
  36         C_STATE_C9,             /* 10 */
  37         C_STATE_C10,            /* 11 */
  38         NUM_C_STATES
  39 };
  40
  41 static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
  42         [C_STATE_C0] = {},
  43         [C_STATE_C1] = {
  44                 .latency = C1_LATENCY,
  45                 .power = C1_POWER,
  46                 .resource = MWAIT_RES(0, 0),
  47         },
  48         [C_STATE_C1E] = {
  49                 .latency = C1_LATENCY,
  50                 .power = C1_POWER,
  51                 .resource = MWAIT_RES(0, 1),
  52         },
  53         [C_STATE_C6_SHORT_LAT] = {
  54                 .latency = C6_LATENCY,
  55                 .power = C6_POWER,
  56                 .resource = MWAIT_RES(2, 0),
  57         },
  58         [C_STATE_C6_LONG_LAT] = {
  59                 .latency = C6_LATENCY,
  60                 .power = C6_POWER,
  61                 .resource = MWAIT_RES(2, 1),
  62         },
  63         [C_STATE_C7_SHORT_LAT] = {
  64                 .latency = C7_LATENCY,
  65                 .power = C7_POWER,
  66                 .resource = MWAIT_RES(3, 0),
  67         },
  68         [C_STATE_C7_LONG_LAT] = {
  69                 .latency = C7_LATENCY,
  70                 .power = C7_POWER,
  71                 .resource = MWAIT_RES(3, 1),
  72         },
  73         [C_STATE_C7S_SHORT_LAT] = {
  74                 .latency = C7_LATENCY,
  75                 .power = C7_POWER,
  76                 .resource = MWAIT_RES(3, 2),
  77         },
  78         [C_STATE_C7S_LONG_LAT] = {
  79                 .latency = C7_LATENCY,
  80                 .power = C7_POWER,
  81                 .resource = MWAIT_RES(3, 3),
  82         },
  83         [C_STATE_C8] = {
  84                 .latency = C8_LATENCY,
  85                 .power = C8_POWER,
  86                 .resource = MWAIT_RES(4, 0),
  87         },
  88         [C_STATE_C9] = {
  89                 .latency = C9_LATENCY,
  90                 .power = C9_POWER,
  91                 .resource = MWAIT_RES(5, 0),
  92         },
  93         [C_STATE_C10] = {
  94                 .latency = C10_LATENCY,
  95                 .power = C10_POWER,
  96                 .resource = MWAIT_RES(6, 0),
  97         },
  98 };
  99
 100 static int cstate_set_non_s0ix[] = {
 101         C_STATE_C1,
 102         C_STATE_C6_LONG_LAT,
 103         C_STATE_C7S_LONG_LAT
 104 };
 105
 106 static int cstate_set_s0ix[] = {
 107         C_STATE_C1,
 108         C_STATE_C7S_LONG_LAT,
 109         C_STATE_C10
 110 };
 111
 112 const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 113 {
 114         static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
 115                                 ARRAY_SIZE(cstate_set_non_s0ix))];
 116         int *set;
 117         int i;
 118
 119         config_t *config = config_of_soc();
 120
 121         int is_s0ix_enable = config->s0ix_enable;
 122
 123         if (is_s0ix_enable) {
 124                 *entries = ARRAY_SIZE(cstate_set_s0ix);
 125                 set = cstate_set_s0ix;
 126         } else {
 127                 *entries = ARRAY_SIZE(cstate_set_non_s0ix);
 128                 set = cstate_set_non_s0ix;
 129         }
 130
 131         for (i = 0; i < *entries; i++) {
 132                 map[i] = cstate_map[set[i]];
 133                 map[i].ctype = i + 1;
 134         }
 135         return map;
 136 }
 137
 138 void soc_power_states_generation(int core_id, int cores_per_package)
 139 {
 140         config_t *config = config_of_soc();
 141
 142         if (config->eist_enable)
 143                 /* Generate P-state tables */
 144                 generate_p_state_entries(core_id, cores_per_package);
 145 }
 146
 147 void soc_fill_fadt(acpi_fadt_t *fadt)
 148 {
 149         const uint16_t pmbase = ACPI_BASE_ADDRESS;
 150
 151         config_t *config = config_of_soc();
 152
 153         fadt->pm_tmr_blk = pmbase + PM1_TMR;
 154         fadt->pm_tmr_len = 4;
 155         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 156         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 157         fadt->x_pm_tmr_blk.bit_offset = 0;
 158         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 159         fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
 160         fadt->x_pm_tmr_blk.addrh = 0x0;
 161
 162         if (config->s0ix_enable)
 163                 fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 164 }
 165
 166 uint32_t soc_read_sci_irq_select(void)
 167 {
 168         return read32p(soc_read_pmc_base() + IRQ_REG);
 169 }
 170
 171 static unsigned long soc_fill_dmar(unsigned long current)
 172 {
 173         uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 174         bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 175
 176         if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
 177                 unsigned long tmp = current;
 178
 179                 current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
 180                 current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0);
 181
 182                 acpi_dmar_drhd_fixup(tmp, current);
 183         }
 184
 185         uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
 186         bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
 187
 188         if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
 189                 unsigned long tmp = current;
 190
 191                 current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
 192                 current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0);
 193
 194                 acpi_dmar_drhd_fixup(tmp, current);
 195         }
 196
 197         /* TCSS Thunderbolt root ports */
 198         for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
 199                 uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
 200                 bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
 201                 if (tbtbar && tbten) {
 202                         unsigned long tmp = current;
 203
 204                         current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
 205                         current += acpi_create_dmar_ds_pci_br(current, 0,
 206                                                               SA_DEV_SLOT_TBT, i);
 207
 208                         acpi_dmar_drhd_fixup(tmp, current);
 209                 }
 210         }
 211
 212         uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
 213         bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
 214
 215         if (vtvc0bar && vtvc0en) {
 216                 const unsigned long tmp = current;
 217
 218                 current += acpi_create_dmar_drhd(current,
 219                                 DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
 220                 current += acpi_create_dmar_ds_ioapic(current,
 221                                 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
 222                                 V_P2SB_CFG_IBDF_FUNC);
 223                 current += acpi_create_dmar_ds_msi_hpet(current,
 224                                 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
 225                                 V_P2SB_CFG_HBDF_FUNC);
 226
 227                 acpi_dmar_drhd_fixup(tmp, current);
 228         }
 229
 230         /* Add RMRR entry */
 231         const unsigned long tmp = current;
 232         current += acpi_create_dmar_rmrr(current, 0,
 233                 sa_get_gsm_base(), sa_get_tolud_base() - 1);
 234         current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0);
 235         acpi_dmar_rmrr_fixup(tmp, current);
 236
 237         return current;
 238 }
 239
 240 unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current,
 241                                    struct acpi_rsdp *rsdp)
 242 {
 243         acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 244
 245         /*
 246          * Create DMAR table only if we have VT-d capability and FSP does not override its
 247          * feature.
 248          */
 249         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
 250             !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
 251                 return current;
 252
 253         printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
 254         acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
 255         current += dmar->header.length;
 256         current = acpi_align_current(current);
 257         acpi_add_table(rsdp, dmar);
 258
 259         return current;
 260 }
 261
 262 void soc_fill_gnvs(struct global_nvs *gnvs)
 263 {
 264         config_t *config = config_of_soc();
 265
 266         /* Enable DPTF based on mainboard configuration */
 267         gnvs->dpte = config->dptf_enable;
 268
 269         /* Set USB2/USB3 wake enable bitmaps. */
 270         gnvs->u2we = config->usb2_wake_enable_bitmap;
 271         gnvs->u3we = config->usb3_wake_enable_bitmap;
 272 }
 273
 274 int soc_madt_sci_irq_polarity(int sci)
 275 {
 276         return MP_IRQ_POLARITY_HIGH;
 277 }