soc/intel/pantherlake: Enable FSP debug log level control using CBFSmain
[coreboot.git] / tests / device / 
treec6cd7f71a5a1ac86264faea14bdeabe1614533bb
drwxr-xr-x   ..
-rw-r--r-- 323 Makefile.mk
-rw-r--r-- 1308 ddr4-test.c
-rw-r--r-- 4066 i2c-test.c