src/include/cpu/amd/msr.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* This file applies to AMD64 products.
   4  * The definitions come from the AMD64 Programmers Manual vol2
   5  * Revision 3.30 and/or the device's BKDG.
   6  */
   7
   8 #ifndef CPU_AMD_MSR_H
   9 #define CPU_AMD_MSR_H
  10
  11 #include <cpu/x86/msr.h>
  12
  13 #define MC4_MISC0                       0x00000413
  14 #define MC4_MISC1                       0xC0000408
  15 #define MC4_MISC2                       0xC0000409
  16 #define FS_Base                         0xC0000100
  17 #define HWCR_MSR                        0xC0010015
  18 #define  SMM_LOCK                       (1 << 0)
  19 #define NB_CFG_MSR                      0xC001001f
  20 #define FidVidStatus                    0xC0010042
  21 #define MC0_CTL_MASK                    0xC0010044
  22 #define MC_CTL_MASK(bank)               (MC0_CTL_MASK + (bank))
  23 #define MSR_INTPEND                     0xC0010055
  24 #define MMIO_CONF_BASE                  0xC0010058
  25 #define  MMIO_RANGE_EN                  (1 << 0)
  26 #define  MMIO_BUS_RANGE_SHIFT           2
  27         /* P-state Current Limit Register */
  28 #define PS_LIM_REG                      0xC0010061
  29          /* P-state Maximum Value shift position */
  30 #define  PS_MAX_VAL_SHFT                4
  31 #define  PS_LIM_MAX_VAL_MASK            (0x7 << PS_MAX_VAL_SHFT)
  32 #define  MAX_PSTATES                    8
  33
  34         /* P-state Control Register */
  35 #define PS_CTL_REG                      0xC0010062
  36          /* P-state Control Register CMD Mask OFF */
  37 #define  PS_CMD_MASK_OFF                ~(7)
  38          /* P-state Status Mask */
  39 #define  PS_STS_MASK                    7
  40         /* P-state Status Register */
  41 #define PS_STS_REG                      0xC0010063
  42 #define PSTATE_0_MSR                    0xC0010064
  43 #define PSTATE_MSR(pstate)              (PSTATE_0_MSR + (pstate))
  44 #define PSTATE_MSR_COUNT                8
  45
  46 #define MSR_PATCH_LOADER                0xC0010020
  47
  48 #define MSR_COFVID_STS                  0xC0010071
  49 #define MSR_CSTATE_ADDRESS              0xC0010073
  50 #define  MSR_CSTATE_ADDRESS_MASK        0xFFFF
  51
  52 #define OSVW_ID_Length                  0xC0010140
  53 #define OSVW_Status                     0xC0010141
  54
  55 #define SMM_BASE_MSR                    0xC0010111
  56 #define SMM_ADDR_MSR                    0xC0010112
  57 #define SMM_MASK_MSR                    0xC0010113
  58 #define  SMM_TSEG_VALID                 (1 << 1)
  59 #define  SMM_TSEG_WB                    (6 << 12)
  60
  61 #define CPU_ID_FEATURES_MSR             0xC0011004
  62 #define CPU_ID_EXT_FEATURES_MSR         0xC0011005
  63 #define CPU_ID_HYPER_EXT_FEATURES       0xC001100d
  64 #define LOGICAL_CPUS_NUM_MSR            0xC001100d
  65 #define LS_CFG_MSR                      0xC0011020
  66 #define IC_CFG_MSR                      0xC0011021
  67 #define DC_CFG_MSR                      0xC0011022
  68 #define BU_CFG_MSR                      0xC0011023
  69 #define FP_CFG_MSR                      0xC0011028
  70 #define DE_CFG_MSR                      0xC0011029
  71 #define BU_CFG2_MSR                     0xC001102A
  72 #define BU_CFG3_MSR                     0xC001102B
  73 #define EX_CFG_MSR                      0xC001102C
  74 #define LS_CFG2_MSR                     0xC001102D
  75 #define IBS_OP_DATA3_MSR                0xC0011037
  76 #define S3_RESUME_EIP_MSR               0xC00110E0
  77 #define PSP_ADDR_MSR                    0xc00110a2
  78
  79 #define CORE_PERF_BOOST_CTRL            0x15c
  80
  81 #endif /* CPU_AMD_MSR_H */