1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Under PCI, each device has 256 bytes of configuration address space,
8 * of which the first 64 bytes are standardized as follows:
10 #define PCI_VENDOR_ID 0x00 /* 16 bits */
11 #define PCI_DEVICE_ID 0x02 /* 16 bits */
12 #define PCI_COMMAND 0x04 /* 16 bits */
13 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
14 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
15 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
16 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
17 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
18 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
19 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
20 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
21 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
22 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
23 #define PCI_COMMAND_INT_DISABLE 0x400 /* Interrupt disable */
25 #define PCI_STATUS 0x06 /* 16 bits */
26 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
27 #define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */
28 /* Support User Definable Features [obsolete] */
29 #define PCI_STATUS_UDF 0x40
30 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
31 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
32 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
33 #define PCI_STATUS_DEVSEL_FAST 0x000
34 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
35 #define PCI_STATUS_DEVSEL_SLOW 0x400
36 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
37 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
38 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
39 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
40 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
42 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
44 #define PCI_REVISION_ID 0x08 /* Revision ID */
45 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
46 #define PCI_CLASS_DEVICE 0x0a /* Device class */
48 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
49 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
50 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
51 #define PCI_HEADER_TYPE_NORMAL 0
52 #define PCI_HEADER_TYPE_BRIDGE 1
53 #define PCI_HEADER_TYPE_CARDBUS 2
55 #define PCI_BIST 0x0f /* 8 bits */
56 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
57 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
58 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
61 * Base addresses specify locations in memory or I/O space.
62 * Decoded size can be determined by writing a value of
63 * 0xffffffff to the register, and reading it back. Only
66 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
67 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
68 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
69 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
70 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
71 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
72 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
73 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
74 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
75 #define PCI_BASE_ADDRESS_MEM_LIMIT_MASK 0x06
76 #define PCI_BASE_ADDRESS_MEM_LIMIT_32 0x00 /* 32 bit address */
77 #define PCI_BASE_ADDRESS_MEM_LIMIT_1M 0x02 /* Below 1M [obsolete] */
78 #define PCI_BASE_ADDRESS_MEM_LIMIT_64 0x04 /* 64 bit address */
79 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
80 #define PCI_BASE_ADDRESS_MEM_ATTR_MASK 0x0f
81 #define PCI_BASE_ADDRESS_IO_ATTR_MASK 0x03
82 /* bit 1 is reserved if address_space = 1 */
84 /* Header type 0 (normal devices) */
85 #define PCI_CARDBUS_CIS 0x28
86 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
87 #define PCI_SUBSYSTEM_ID 0x2e
88 /* Bits 31..11 are address, 10..1 reserved */
89 #define PCI_ROM_ADDRESS 0x30
90 #define PCI_ROM_ADDRESS_ENABLE 0x01
91 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
93 /* Offset of first capability list entry */
94 #define PCI_CAPABILITY_LIST 0x34
96 /* 0x35-0x3b are reserved */
97 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
98 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
99 #define PCI_MIN_GNT 0x3e /* 8 bits */
100 #define PCI_MAX_LAT 0x3f /* 8 bits */
102 /* Header type 1 (PCI-to-PCI bridges) */
103 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
104 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
105 /* Highest bus number behind the bridge */
106 #define PCI_SUBORDINATE_BUS 0x1a
107 /* Latency timer for secondary interface */
108 #define PCI_SEC_LATENCY_TIMER 0x1b
109 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
110 #define PCI_IO_LIMIT 0x1d
111 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
112 #define PCI_IO_RANGE_TYPE_16 0x00
113 #define PCI_IO_RANGE_TYPE_32 0x01
114 #define PCI_IO_RANGE_MASK ~0x0f
115 /* Secondary status register, only bit 14 used */
116 #define PCI_SEC_STATUS 0x1e
117 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
118 #define PCI_MEMORY_LIMIT 0x22
119 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
120 #define PCI_MEMORY_RANGE_MASK ~0x0f
121 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
122 #define PCI_PREF_MEMORY_LIMIT 0x26
123 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
124 #define PCI_PREF_RANGE_TYPE_32 0x00
125 #define PCI_PREF_RANGE_TYPE_64 0x01
126 #define PCI_PREF_RANGE_MASK ~0x0f
127 /* Upper half of prefetchable memory range */
128 #define PCI_PREF_BASE_UPPER32 0x28
129 #define PCI_PREF_LIMIT_UPPER32 0x2c
130 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
131 #define PCI_IO_LIMIT_UPPER16 0x32
132 /* 0x34 same as for htype 0 */
133 /* 0x35-0x3b is reserved */
134 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
135 #define PCI_ROM_ADDRESS1 0x38
136 /* 0x3c-0x3d are same as for htype 0 */
137 #define PCI_BRIDGE_CONTROL 0x3e
138 /* Enable parity detection on secondary interface */
139 #define PCI_BRIDGE_CTL_PARITY 0x01
140 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
141 #define PCI_BRIDGE_CTL_ISA 0x04 /* Disable bridging of ISA ports */
142 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
143 #define PCI_BRIDGE_CTL_VGA16 0x10 /* Enable 16-bit i/o port decoding */
144 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
145 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
146 /* Fast Back2Back enabled on secondary interface */
147 #define PCI_BRIDGE_CTL_FAST_BACK 0x80
149 /* Header type 2 (CardBus bridges) */
150 #define PCI_CB_CAPABILITY_LIST 0x14
152 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
153 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
154 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
155 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
156 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
157 #define PCI_CB_MEMORY_BASE_0 0x1c
158 #define PCI_CB_MEMORY_LIMIT_0 0x20
159 #define PCI_CB_MEMORY_BASE_1 0x24
160 #define PCI_CB_MEMORY_LIMIT_1 0x28
161 #define PCI_CB_IO_BASE_0 0x2c
162 #define PCI_CB_IO_BASE_0_HI 0x2e
163 #define PCI_CB_IO_LIMIT_0 0x30
164 #define PCI_CB_IO_LIMIT_0_HI 0x32
165 #define PCI_CB_IO_BASE_1 0x34
166 #define PCI_CB_IO_BASE_1_HI 0x36
167 #define PCI_CB_IO_LIMIT_1 0x38
168 #define PCI_CB_IO_LIMIT_1_HI 0x3a
169 #define PCI_CB_IO_RANGE_MASK ~0x03
170 /* 0x3c-0x3d are same as for htype 0 */
171 #define PCI_CB_BRIDGE_CONTROL 0x3e
172 /* Similar to standard bridge control register */
173 #define PCI_CB_BRIDGE_CTL_PARITY 0x01
174 #define PCI_CB_BRIDGE_CTL_SERR 0x02
175 #define PCI_CB_BRIDGE_CTL_ISA 0x04
176 #define PCI_CB_BRIDGE_CTL_VGA 0x08
177 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
178 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
179 /* Enable interrupt for 16-bit cards */
180 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
181 /* Prefetch enable for both memory regions */
182 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
183 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
184 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
185 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
186 #define PCI_CB_SUBSYSTEM_ID 0x42
187 /* 16-bit PC Card legacy mode base address (ExCa) */
188 #define PCI_CB_LEGACY_MODE_BASE 0x44
189 /* 0x48-0x7f reserved */
191 /* Capability lists */
193 #define PCI_CAP_LIST_ID 0 /* Capability ID */
194 #define PCI_CAP_ID_PM 0x01 /* Power Management */
195 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
196 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
197 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
198 #define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */
199 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
200 #define PCI_CAP_ID_PCIX 0x07 /* PCIX */
201 #define PCI_CAP_ID_HT 0x08 /* Hypertransport */
202 #define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */
203 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
204 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
205 #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */
206 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
207 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
208 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
210 /* Hypertransport Registers */
211 #define PCI_HT_CAP_SIZEOF 4
212 #define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */
213 #define PCI_HT_CAP_HOST_WIDTH 6 /* width value & capability */
214 #define PCI_HT_CAP_HOST_FREQ 0x09 /* Host frequency */
215 #define PCI_HT_CAP_HOST_FREQ_CAP 0x0a /* Host Frequency capability */
216 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
217 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
218 #define PCI_HT_CAP_SLAVE_WIDTH0 6 /* width value & capability */
219 #define PCI_HT_CAP_SLAVE_WIDTH1 0x0a /* width value & capability to */
220 #define PCI_HT_CAP_SLAVE_FREQ0 0x0d /* Slave frequency from */
221 #define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */
222 #define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e /* Frequency capability from */
223 #define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12 /* Frequency capability to */
224 #define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Link Enumeration Scratchpad */
226 /* Power Management Registers */
228 #define PCI_PM_PMC 2 /* PM Capabilities Register */
229 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
230 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
231 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxiliary power support */
232 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
233 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
234 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
235 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
236 #define PCI_PM_CTRL 4 /* PM control and status register */
237 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
238 #define PCI_PM_CTRL_POWER_STATE_D0 0x0
239 #define PCI_PM_CTRL_POWER_STATE_D1 0x1
240 #define PCI_PM_CTRL_POWER_STATE_D2 0x2
241 #define PCI_PM_CTRL_POWER_STATE_D3HOT 0x3
242 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
243 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
244 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
245 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
246 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
247 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
248 /* Bus power/clock control enable (??) */
249 #define PCI_PM_BPCC_ENABLE 0x80
250 #define PCI_PM_DATA_REGISTER 7 /* (??) */
251 #define PCI_PM_SIZEOF 8
255 #define PCI_AGP_VERSION 2 /* BCD version number */
256 #define PCI_AGP_RFU 3 /* Rest of capability flags */
257 #define PCI_AGP_STATUS 4 /* Status register */
258 /* Maximum number of requests - 1 */
259 #define PCI_AGP_STATUS_RQ_MASK 0xff000000
260 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
261 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
262 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
263 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
264 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
265 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
266 #define PCI_AGP_COMMAND 8 /* Control register */
267 /* Master: Maximum number of requests */
268 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000
269 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
270 /* Allow processing of AGP transactions */
271 #define PCI_AGP_COMMAND_AGP 0x0100
272 /* Allow processing of 64-bit addresses */
273 #define PCI_AGP_COMMAND_64BIT 0x0020
274 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
275 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
276 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
277 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
278 #define PCI_AGP_SIZEOF 12
280 /* Slot Identification */
282 #define PCI_SID_ESR 2 /* Expansion Slot Register */
283 /* Number of expansion slots available */
284 #define PCI_SID_ESR_NSLOTS 0x1f
285 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
286 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
288 /* Message Signaled Interrupts registers */
290 #define PCI_MSI_FLAGS 2 /* Various flags */
291 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
292 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
293 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
294 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
295 #define PCI_MSI_RFU 3 /* Rest of capability flags */
296 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
297 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
298 #define PCI_MSI_ADDRESS_HI 8
299 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
300 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
301 #define PCI_MSI_MASK_BIT 16 /* Mask bits register */
303 /* MSI-X registers */
304 #define PCI_MSIX_FLAGS 2
305 #define PCI_MSIX_FLAGS_QSIZE 0x7FF /* table size */
306 #define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
307 #define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
308 #define PCI_MSIX_TABLE 4 /* Table offset */
309 #define PCI_MSIX_PBA 8 /* Pending Bit Array offset */
310 #define PCI_MSIX_PBA_BIR 0x7 /* BAR index */
311 #define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */
312 #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
314 /* CompactPCI Hotswap Register */
316 #define PCI_CHSWP_CSR 2 /* Control and Status Register */
317 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
318 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
319 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
320 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */
321 #define PCI_CHSWP_PI 0x30 /* Programming Interface */
322 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
323 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
325 /* PCI-X registers */
327 #define PCI_X_CMD 2 /* Modes & Features */
328 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
329 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
330 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
331 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
332 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
333 #define PCI_X_STATUS 4 /* PCI-X capabilities */
334 #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
335 #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
336 #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
337 #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
338 #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
339 /* Unexpected Split Completion */
340 #define PCI_X_STATUS_UNX_SPL 0x00080000
341 #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
342 /* Designed Max Memory Read Count */
343 #define PCI_X_STATUS_MAX_READ 0x00600000
344 /* Designed Max Cumulative Read Size */
345 #define PCI_X_STATUS_MAX_SPLIT 0x03800000
346 /* Rcvd Split Completion Error Msg */
347 #define PCI_X_STATUS_SPL_ERR 0x20000000
348 #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
349 #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
351 /* PCI-X bridge registers */
352 #define PCI_X_SEC_STATUS 2 /* Secondary status */
353 /* The bus behind the bridge is 64bits wide */
354 #define PCI_X_SSTATUS_64BIT 0x0001
355 /* The bus behind the bridge is 133Mhz Capable */
356 #define PCI_X_SSTATUS_133MHZ 0x0002
357 #define PCI_X_SSTATUS_SPL_DISC 0x0004 /* Split Completion Discarded */
358 #define PCI_X_SSTATUS_UNX_SPL 0x0008 /* Unexpected Split Completion */
359 #define PCI_X_SSTATUS_SPL_OVR 0x0010 /* Split Completion Overrun */
360 #define PCI_X_SSTATUS_SPL_DLY 0x0020 /* Split Completion Delayed */
361 /* PCI-X mode and frequency */
362 #define PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6)
363 #define PCI_X_SSTATUS_CONVENTIONAL_PCI 0x0
364 #define PCI_X_SSTATUS_MODE1_66MHZ 0x1
365 #define PCI_X_SSTATUS_MODE1_100MHZ 0x2
366 #define PCI_X_SSTATUS_MODE1_133MHZ 0x3
367 #define PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ 0x9
368 #define PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ 0xa
369 #define PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ 0xb
370 #define PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ 0xd
371 #define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ 0xe
372 #define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ 0xf
373 #define PCI_X_SSTATUS_VERSION(x) (((x) >> 12) & 3) /* Version */
374 /* The bus behind the bridge is 266Mhz Capable */
375 #define PCI_X_SSTATUS_266MHZ 0x4000
376 /* The bus behind the bridge is 533Mhz Capable */
377 #define PCI_X_SSTAUTS_533MHZ 0x8000
379 /* PCI Express capability registers */
381 #define PCI_EXP_FLAGS 2 /* Capabilities register */
382 #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
383 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
384 #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
385 #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
386 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
387 #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
388 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
389 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
390 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
391 #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
392 #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
393 #define PCI_EXP_DEVCAP 4 /* Device capabilities */
394 #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
395 #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
396 #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
397 #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
398 #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
399 #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
400 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
401 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
402 #define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
403 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
404 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
405 #define PCI_EXP_DEVCTL 8 /* Device Control */
406 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
407 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
408 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
409 #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
410 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
411 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
412 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
413 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
414 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
415 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
416 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
417 #define PCI_EXP_DEVSTA 10 /* Device Status */
418 #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
419 #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
420 #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
421 #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
422 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
423 #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
424 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
425 #define PCI_EXP_LNKCAP_MLS 0x000f /* Maximum Link Speed */
426 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
427 #define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
428 #define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
429 #define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
430 #define PCI_EXP_CLK_PM 0x40000 /* Clock Power Management */
431 #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
432 #define PCI_EXP_LNKCTL 16 /* Link Control */
433 #define PCI_EXP_LNKCTL_LD 0x10 /* Link Disable */
434 #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */
435 #define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock Configuration */
436 #define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */
437 #define PCI_EXP_LNKSTA 18 /* Link Status */
438 #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
439 #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
440 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
441 #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
442 #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
443 #define PCI_EXP_SLTCAP_SPLV 0x7f80 /* Slot Power Limit Value */
444 #define PCI_EXP_SLTCAP_SPLS 0x18000 /* Slot Power Limit Scale */
445 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
446 #define PCI_EXP_SLTCTL 24 /* Slot Control */
447 #define PCI_EXP_SLTSTA 26 /* Slot Status */
448 #define PCI_EXP_SLTSTA_PDS 0x40 /* Presence Detect Status */
449 #define PCI_EXP_RTCTL 28 /* Root Control */
450 #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
451 #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
452 #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
453 #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
454 #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
455 #define PCI_EXP_RTCAP 30 /* Root Capabilities */
456 #define PCI_EXP_RTSTA 32 /* Root Status */
457 #define PCI_EXP_DEVCAP2 36 /* Device capabilities 2 */
458 #define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */
459 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
460 #define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */
462 /* Extended Capabilities (PCI-X 2.0 and Express) */
463 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
464 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
465 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
467 #define PCI_EXT_CAP_ID_ERR 1
468 #define PCI_EXT_CAP_ID_VC 2
469 #define PCI_EXT_CAP_ID_DSN 3
470 #define PCI_EXT_CAP_ID_PWR 4
471 #define PCI_EXT_CAP_ID_VNDR 0x0b
473 /* Extended Capability lists*/
474 #define PCIE_EXT_CAP_OFFSET 0x100
475 #define PCIE_EXT_CAP_AER_ID 0x0001
476 #define PCIE_EXT_CAP_ID_ATS 0x000F
477 #define PCIE_EXT_CAP_L1SS_ID 0x001E
478 #define PCIE_EXT_CAP_LTR_ID 0x0018
479 #define PCIE_EXT_CAP_RESIZABLE_BAR 0x0015
480 #define PCIE_EXT_CAP_RCECEA_ID 0x0007
481 #define PCIE_EXT_CAP_SRIOV_ID 0x0010
483 /* Secondary PCI Express Extended Capability Structure */
484 #define PCI_EXP_SEC_CAP_ID 0x19
485 #define PCI_EXP_SEC_LNK_CTL3 4 /* Link Control 3 */
486 #define PCI_EXP_SEC_LANE_ERR_STATUS 8 /* Lane Error Status */
488 /* Advanced Error Reporting */
489 #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
490 #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
491 #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
492 #define PCI_ERR_SURPRISE_DN 0x00000020 /* Surprise Down */
493 #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
494 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
495 #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
496 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
497 #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
498 #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
499 #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
500 #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
501 #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
502 #define PCI_ERR_UNC_INTL_ERR 0x00400000 /* Uncorrectable Internal Error */
503 #define PCI_ERR_UNC_POISON_BLK 0x04000000 /* Poisoned TLP Egress Blocked */
504 #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
505 /* Same bits as above */
506 #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
507 /* Same bits as above */
508 #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
509 #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
510 #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
511 #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
512 #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
513 #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
514 #define PCI_ERR_COR_ANF 0x00002000 /* Advisory Non-Fatal Error */
515 #define PCI_ERR_COR_INTL_ERR 0x00004000 /* Corrected Internal Error */
516 #define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow Error */
517 #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
518 /* Same bits as above */
519 #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
520 #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
521 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
522 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
523 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
524 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
525 #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
526 #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
527 #define PCI_EXP_ROOT_CERE 0x0001 /* Correctable Error Reporting Enable */
528 #define PCI_EXP_ROOT_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
529 #define PCI_EXP_ROOT_FERE 0x0004 /* Fatal Error Reporting Enable */
530 #define PCI_ERR_ROOT_STATUS 48
531 #define PCI_ERR_ROOT_COR_SRC 52
532 #define PCI_ERR_ROOT_SRC 54
534 /* DPC Capability Structure */
535 #define PCIE_DPC_CAP_ID 0x1d
536 #define PCIE_DPC_CTL 0x6
537 #define DPC_TRIGGER_EN (1 << 1)
538 #define DPC_INT_EN (1 << 3)
539 #define DPC_ERR_COR_EN (1 << 4)
540 #define DPC_POISON_TLP (1 << 5)
541 #define PCIE_DPC_RP_PIO_MASK 0x10
542 #define PCIE_DPC_SEV 0x14
544 /* Virtual Channel */
545 #define PCI_VC_PORT_REG1 4
546 #define PCI_VC_PORT_REG2 8
547 #define PCI_VC_PORT_CTRL 12
548 #define PCI_VC_PORT_STATUS 14
549 #define PCI_VC_RES_CAP 16
550 #define PCI_VC_RES_CTRL 20
551 #define PCI_VC_RES_STATUS 26
553 /* Power Budgeting */
554 #define PCI_PWR_DSR 4 /* Data Select Register */
555 #define PCI_PWR_DATA 8 /* Data Register */
556 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
557 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
558 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
559 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
560 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
561 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
562 #define PCI_PWR_CAP 12 /* Capability */
563 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
565 /* Latency Tolerance Reporting */
566 #define PCI_LTR_MAX_SNOOP 4
567 #define PCI_LTR_MAX_NOSNOOP 6
569 /* PCIe Resizable BARs */
570 #define PCI_REBAR_CAP_OFFSET 0x4
571 #define PCI_REBAR_CAP_SIZE_MASK 0xfffffff0
572 #define PCI_REBAR_CTRL_OFFSET 0x8
573 #define PCI_REBAR_CTRL_NBARS_MASK 0xe0
574 #define PCI_REBAR_CTRL_NBARS_SHIFT 5
575 #define PCI_REBAR_CTRL_IDX_MASK 0x07
576 #define PCI_REBAR_CTRL_SIZE_MASK 0xffff0000
577 #define PCI_REBAR_CTRL_SIZE_SHIFT 16
579 /* Root Complex Event Collector Endpoint Association */
580 #define PCI_RCECEA_BITMAP 4
581 #define PCI_RCECEA_BUSNUM 8
584 * Single Root IO Virtualization
585 * Section 9.3 of PCI Express Base Specification Revision 6.2.
587 #define PCIE_EXT_CAP_SRIOV_TOTAL_VFS 0x0e
588 #define PCIE_EXT_CAP_SRIOV_SUPPORTED_PAGE_SIZE 0x1c
589 #define PCIE_EXT_CAP_SRIOV_SYSTEM_PAGE_SIZE 0x20
590 #define PCIE_EXT_CAP_SRIOV_VF_BAR0 0x24
591 #define PCIE_EXT_CAP_SRIOV_VF_BAR5 0x38
594 * The PCI interface treats multi-function devices as independent
595 * devices. The slot/function address of each device is encoded
596 * in a single byte as follows:
601 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
602 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
603 #define PCI_FUNC(devfn) ((devfn) & 0x07)
606 * CONFIG_ECAM_MMCONF_BUS_NUMBER is a power of 2. For values <= 256,
607 * PCI_BUSES_PER_SEGMENT_GROUP is CONFIG_ECAM_MMCONF_BUS_NUMBER and PCI_SEGMENT_GROUP_COUNT
608 * is 1. For values > 256, PCI_BUSES_PER_SEGMENT_GROUP is 256 and PCI_SEGMENT_GROUP_COUNT is
609 * CONFIG_ECAM_MMCONF_BUS_NUMBER / 256.
611 #define PCI_BUS_NUMBER_MASK 0xff
612 #define PCI_SEGMENT_GROUP_COUNT (((CONFIG_ECAM_MMCONF_BUS_NUMBER - 1) >> 8) + 1)
613 #define PCI_BUSES_PER_SEGMENT_GROUP (((CONFIG_ECAM_MMCONF_BUS_NUMBER - 1) & PCI_BUS_NUMBER_MASK) + 1)
614 #define PCI_PER_SEGMENT_GROUP_ECAM_SIZE (256 * MiB)
616 /* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */
617 #define PCI_DEV2DEVFN(sdev) (((sdev)>>12) & 0xff)
618 #define PCI_DEV2SEGBUS(sdev) (((sdev)>>20) & 0xfff)
619 #define PCI_DEV2BUS(sdev) (((sdev)>>20) & PCI_BUS_NUMBER_MASK)
620 #define PCI_DEV2SEG(sdev) (((sdev)>>28) & 0xf)
622 /* Fields from within the device's class value. */
623 #define PCI_CLASS_GET_DEVICE(c) (c >> 8)
624 #define PCI_CLASS_GET_PROG(c) (c & 0xff)
626 #endif /* PCI_DEF_H */
