src/include/spd_bin.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SPD_BIN_H
   4 #define SPD_BIN_H
   5
   6 #include <device/dram/ddr3.h>
   7 #include <stdint.h>
   8 #include <commonlib/region.h>
   9
  10 #define SPD_PAGE_LEN            256
  11 #define SPD_PAGE_LEN_DDR4       512
  12 #define SPD_PAGE_0              (0x6C >> 1)
  13 #define SPD_PAGE_1              (0x6E >> 1)
  14 #define SPD_DRAM_TYPE           2
  15 #define  SPD_DRAM_DDR3          0x0B
  16 #define  SPD_DRAM_LPDDR3_INTEL  0xF1
  17 #define  SPD_DRAM_LPDDR3_JEDEC  0x0F
  18 #define  SPD_DRAM_DDR4          0x0C
  19 #define  SPD_DRAM_LPDDR4        0x10
  20 #define  SPD_DRAM_LPDDR4X       0x11
  21 #define  SPD_DRAM_DDR5          0x12
  22 #define  SPD_DRAM_LPDDR5        0x13
  23 #define  SPD_DRAM_LPDDR5X       0x15
  24 #define SPD_DENSITY_BANKS       4
  25 #define SPD_ADDRESSING          5
  26 #define SPD_SN_LEN              4
  27 #define DDR3_ORGANIZATION       7
  28 #define DDR3_BUS_DEV_WIDTH      8
  29 #define DDR4_ORGANIZATION       12
  30 #define DDR4_BUS_DEV_WIDTH      13
  31 #define DDR3_SPD_PART_OFF       SPD_DDR3_PART_NUM
  32 #define DDR3_SPD_PART_LEN       SPD_DDR3_PART_LEN
  33 #define DDR3_SPD_SN_OFF         122
  34 #define LPDDR3_SPD_PART_OFF     SPD_DDR3_PART_NUM
  35 #define LPDDR3_SPD_PART_LEN     SPD_DDR3_PART_LEN
  36 #define DDR4_SPD_PART_OFF       329
  37 #define DDR4_SPD_PART_LEN       20
  38 #define DDR4_SPD_SN_OFF         325
  39
  40 struct spd_block {
  41         u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
  42         u8 *spd_array[CONFIG_DIMM_MAX];
  43         /* Length of each dimm */
  44         u16 len;
  45 };
  46
  47 void print_spd_info(uint8_t spd[]);
  48 uintptr_t spd_cbfs_map(u8 spd_index);
  49 void dump_spd_info(struct spd_block *blk);
  50 void get_spd_smbus(struct spd_block *blk);
  51
  52 /*
  53  * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4.
  54  *  return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present.
  55  *  return CB_ERR, if dram_type is not supported or addr is a zero.
  56  */
  57 enum cb_err get_spd_sn(u8 addr, u32 *sn);
  58
  59 /* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and
  60    verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */
  61 int read_ddr3_spd_from_cbfs(u8 *buf, int idx);
  62 #endif