src/northbridge/intel/gm45/Makefile.mk

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y)
   4
   5 bootblock-y += bootblock.c
   6
   7 romstage-y += early_init.c
   8 romstage-y += early_reset.c
   9 romstage-y += raminit.c
  10 romstage-y += raminit_rcomp_calibration.c
  11 romstage-y += raminit_receive_enable_calibration.c
  12 romstage-y += raminit_read_write_training.c
  13 romstage-y += raminit_meminfo.c
  14 romstage-y += pcie.c
  15 romstage-y += thermal.c
  16 romstage-y += igd.c
  17 romstage-y += pm.c
  18 romstage-y += memmap.c
  19 romstage-y += iommu.c
  20 romstage-y += romstage.c
  21
  22 ramstage-y += acpi.c
  23
  24 ramstage-y += memmap.c
  25 ramstage-y += northbridge.c
  26 ramstage-y += gma.c
  27
  28 postcar-y += memmap.c
  29
  30 endif