src/northbridge/intel/gm45/thermal.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <spd.h>
   6
   7 #include "gm45.h"
   8
   9 void raminit_thermal(const sysinfo_t *sysinfo)
  10 {
  11         const mem_clock_t freq = sysinfo->selected_timings.mem_clock;
  12         int x;
  13         FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, x) {
  14                 const chip_width_t width = sysinfo->dimms[x].chip_width;
  15                 const chip_capacity_t size = sysinfo->dimms[x].chip_capacity;
  16                 if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x16)) {
  17                         mchbar_write32(CxDTPEW(x), 0x0d0b0403);
  18                         mchbar_write32(CxDTPEW(x) + 4, 0x060d);
  19                         mchbar_write32(CxDTAEW(x), 0x2d0b221a);
  20                         mchbar_write32(CxDTAEW(x) + 4, 0xc779956e);
  21                 } else
  22                 if ((freq == MEM_CLOCK_1067MT) && (width == CHIP_WIDTH_x8)) {
  23                         mchbar_write32(CxDTPEW(x), 0x06040101);
  24                         mchbar_write32(CxDTPEW(x) + 4, 0x0506);
  25                         if (size == CHIP_CAP_2G)
  26                                 mchbar_write32(CxDTAEW(x), 0xa1071416);
  27                         else
  28                                 mchbar_write32(CxDTAEW(x), 0x1a071416);
  29                         mchbar_write32(CxDTAEW(x) + 4, 0x7246643f);
  30                 } else
  31                 if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x16)) {
  32                         mchbar_write32(CxDTPEW(x), 0x06030100);
  33                         mchbar_write32(CxDTPEW(x) + 4, 0x0506);
  34                         mchbar_write32(CxDTAEW(x), 0x3e081714);
  35                         mchbar_write32(CxDTAEW(x) + 4, 0xbb79a171);
  36                 } else
  37                 if ((freq == MEM_CLOCK_800MT) && (width == CHIP_WIDTH_x8)) {
  38                         if (size <= CHIP_CAP_512M)
  39                                 mchbar_write32(CxDTPEW(x), 0x05050101);
  40                         else
  41                                 mchbar_write32(CxDTPEW(x), 0x05060101);
  42                         mchbar_write32(CxDTPEW(x) + 4, 0x0503);
  43                         if (size == CHIP_CAP_2G) {
  44                                 mchbar_write32(CxDTAEW(x), 0x57051010);
  45                                 mchbar_write32(CxDTAEW(x) + 4, 0x5fd15dde);
  46                         } else
  47                         if (size == CHIP_CAP_1G) {
  48                                 mchbar_write32(CxDTAEW(x), 0x3306130e);
  49                                 mchbar_write32(CxDTAEW(x) + 4, 0x5763485d);
  50                         } else
  51                         if (size <= CHIP_CAP_512M) {
  52                                 mchbar_write32(CxDTAEW(x), 0x1e08170d);
  53                                 mchbar_write32(CxDTAEW(x) + 4, 0x502f3827);
  54                         }
  55                 } else
  56                 if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x16)) {
  57                         mchbar_write32(CxDTPEW(x), 0x02000000);
  58                         mchbar_write32(CxDTPEW(x) + 4, 0x0402);
  59                         mchbar_write32(CxDTAEW(x), 0x46061111);
  60                         mchbar_write32(CxDTAEW(x) + 4, 0xb579a772);
  61                 } else
  62                 if ((freq == MEM_CLOCK_667MT) && (width == CHIP_WIDTH_x8)) {
  63                         mchbar_write32(CxDTPEW(x), 0x04070101);
  64                         mchbar_write32(CxDTPEW(x) + 4, 0x0501);
  65                         if (size == CHIP_CAP_2G) {
  66                                 mchbar_write32(CxDTAEW(x), 0x32040e0d);
  67                                 mchbar_write32(CxDTAEW(x) + 4, 0x55ff59ff);
  68                         } else
  69                         if (size == CHIP_CAP_1G) {
  70                                 mchbar_write32(CxDTAEW(x), 0x3f05120a);
  71                                 mchbar_write32(CxDTAEW(x) + 4, 0x49713a6c);
  72                         } else
  73                         if (size <= CHIP_CAP_512M) {
  74                                 mchbar_write32(CxDTAEW(x), 0x20081808);
  75                                 mchbar_write32(CxDTAEW(x) + 4, 0x3f23221b);
  76                         }
  77                 }
  78
  79                 /* also L-Shaped */
  80                 if (sysinfo->selected_timings.channel_mode ==
  81                                 CHANNEL_MODE_DUAL_INTERLEAVED) {
  82                         if (freq == MEM_CLOCK_1067MT) {
  83                                 mchbar_write32(CxGTEW(x), 0xc8f81717);
  84                         } else
  85                         if (freq == MEM_CLOCK_800MT) {
  86                                 mchbar_write32(CxGTEW(x), 0x96ba1717);
  87                         } else
  88                         if (freq == MEM_CLOCK_667MT) {
  89                                 mchbar_write32(CxGTEW(x), 0x7d9b1717);
  90                         }
  91                 } else {
  92                         if (freq == MEM_CLOCK_1067MT) {
  93                                 mchbar_write32(CxGTEW(x), 0x53661717);
  94                         } else
  95                         if (freq == MEM_CLOCK_800MT) {
  96                                 mchbar_write32(CxGTEW(x), 0x886e1717);
  97                         } else
  98                         if (freq == MEM_CLOCK_667MT) {
  99                                 mchbar_write32(CxGTEW(x), 0x38621717);
 100                         }
 101                 }
 102         }
 103
 104         // always?
 105         mchbar_write32(CxDTC(0), 0x00004020);
 106         mchbar_write32(CxDTC(1), 0x00004020);
 107         mchbar_write32(CxGTC(0), 0x00304848);
 108         mchbar_write32(CxGTC(1), 0x00304848);
 109
 110         /* enable thermal sensors */
 111         u32 tmp;
 112         tmp = mchbar_read32(0x1290) & 0xfff8;
 113         mchbar_write32(0x1290, tmp | 0xa4810007);
 114         tmp = mchbar_read32(0x1390) & 0xfff8;
 115         mchbar_write32(0x1390, tmp | 0xa4810007);
 116         tmp = mchbar_read32(0x12b4) & 0xfff8;
 117         mchbar_write32(0x12b4, tmp | 0xa2810007);
 118         tmp = mchbar_read32(0x13b4) & 0xfff8;
 119         mchbar_write32(0x13b4, tmp | 0xa2810007);
 120         mchbar_write8(0x1070, 1);
 121         mchbar_write8(0x1080, 6);
 122         if (sysinfo->gfx_type == GMCH_PM45) {
 123                 mchbar_write16(0x1001, 0);
 124                 mchbar_write8(0x1007, 0);
 125                 mchbar_write32(0x1010, 0);
 126                 mchbar_write32(0x1014, 0);
 127                 mchbar_write8(0x101c, 0x98);
 128                 mchbar_write16(0x1041, 0x9200);
 129                 mchbar_write8(0x1047, 0);
 130                 mchbar_write32(0x1050, 0x2309);
 131                 mchbar_write32(0x1054, 0);
 132                 mchbar_write8(0x105c, 0x98);
 133         } else {
 134                 mchbar_write16(0x1001, 0x9200);
 135                 mchbar_write8(0x1007, 0);
 136                 mchbar_write32(0x1010, 0x2309);
 137                 mchbar_write32(0x1014, 0);
 138                 mchbar_write8(0x101c, 0x98);
 139                 mchbar_write16(0x1041, 0);
 140                 mchbar_write8(0x1047, 0);
 141                 mchbar_write32(0x1050, 0);
 142                 mchbar_write32(0x1054, 0);
 143                 mchbar_write8(0x105c, 0x98);
 144         }
 145
 146         mchbar_setbits32(0x1010, 1 << 31);
 147         mchbar_setbits32(0x1050, 1 << 31);
 148         mchbar_setbits32(CxGTC(0), 1 << 31);
 149         mchbar_setbits32(CxGTC(1), 1 << 31);
 150
 151         if (sysinfo->gs45_low_power_mode) {
 152                 mchbar_write32(0x11b0, 0xa000083a);
 153         } else if (sysinfo->gfx_type == GMCH_GM49) {
 154                 mchbar_write32(0x11b0, 0x2000383a);
 155                 mchbar_clrbits16(0x1190, 1 << 15);
 156         } else if ((sysinfo->gfx_type != GMCH_PM45) &&
 157                         (sysinfo->gfx_type != GMCH_UNKNOWN)) {
 158                 mchbar_write32(0x11b0, 0xa000383a);
 159         }
 160
 161         switch (sysinfo->selected_timings.fsb_clock) {
 162         case FSB_CLOCK_667MHz:
 163                 mchbar_write32(0x11d0, 0x0fd88000);
 164                 break;
 165         case FSB_CLOCK_800MHz:
 166                 mchbar_write32(0x11d0, 0x1303c000);
 167                 break;
 168         case FSB_CLOCK_1067MHz:
 169                 mchbar_write32(0x11d0, 0x194a0000);
 170                 break;
 171         }
 172         tmp = mchbar_read32(0x11d4) & ~0x1f;
 173         mchbar_write32(0x11d4, tmp | 4);
 174 }