src/northbridge/intel/i440bx/northbridge.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <cpu/x86/mp.h>
   5 #include <device/pci_ops.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <stdint.h>
  10 #include "i440bx.h"
  11
  12 static void northbridge_init(struct device *dev)
  13 {
  14         printk(BIOS_SPEW, "Northbridge Init\n");
  15 }
  16
  17 static struct device_operations northbridge_operations = {
  18         .read_resources   = pci_dev_read_resources,
  19         .set_resources    = pci_dev_set_resources,
  20         .enable_resources = pci_dev_enable_resources,
  21         .init             = northbridge_init,
  22 };
  23
  24 static const struct pci_driver northbridge_driver __pci_driver = {
  25         .ops = &northbridge_operations,
  26         .vendor = PCI_VID_INTEL,
  27         .device = 0x7190,
  28 };
  29
  30 static void i440bx_domain_read_resources(struct device *dev)
  31 {
  32         struct device *mc_dev;
  33         uint32_t pci_tolm;
  34
  35         pci_domain_read_resources(dev);
  36
  37         pci_tolm = find_pci_tolm(dev->downstream);
  38         mc_dev = dev->downstream->children;
  39         if (mc_dev) {
  40                 unsigned long tomk, tolmk;
  41                 int idx;
  42
  43                 /* Figure out which areas are/should be occupied by RAM. The
  44                  * value of the highest DRB denotes the end of the physical
  45                  * memory (in units of 8MB).
  46                  */
  47                 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
  48
  49                 /* Convert to KB. */
  50                 tomk *= (8 * 1024);
  51
  52                 printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024);
  53
  54                 /* Compute the top of low memory. */
  55                 tolmk = pci_tolm / 1024;
  56
  57                 if (tolmk >= tomk) {
  58                         /* The PCI hole does not overlap the memory. */
  59                         tolmk = tomk;
  60                 }
  61
  62                 /* Report the memory regions. */
  63                 idx = 10;
  64                 ram_range(dev, idx++, 0, 0xa0000);
  65                 ram_from_to(dev, idx++, 0xc0000, tolmk * KiB);
  66         }
  67 }
  68
  69 static struct device_operations pci_domain_ops = {
  70         .read_resources         = i440bx_domain_read_resources,
  71         .set_resources          = pci_domain_set_resources,
  72         .scan_bus               = pci_host_bridge_scan_bus,
  73 };
  74
  75 static int get_cpu_count(void)
  76 {
  77         return CONFIG_MAX_CPUS;
  78 }
  79
  80 static const struct mp_ops mp_ops = {
  81         .get_cpu_count = get_cpu_count,
  82 };
  83
  84 void mp_init_cpus(struct bus *cpu_bus)
  85 {
  86         /* TODO: Handle mp_init_with_smm failure? */
  87         mp_init_with_smm(cpu_bus, &mp_ops);
  88 }
  89
  90 static struct device_operations cpu_bus_ops = {
  91         .read_resources   = noop_read_resources,
  92         .set_resources    = noop_set_resources,
  93         .init             = mp_cpu_bus_init,
  94 };
  95
  96 static void enable_dev(struct device *dev)
  97 {
  98         /* Set the operations if it is a special bus type */
  99         if (dev->path.type == DEVICE_PATH_DOMAIN) {
 100                 dev->ops = &pci_domain_ops;
 101         }
 102         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
 103                 dev->ops = &cpu_bus_ops;
 104         }
 105 }
 106
 107 struct chip_operations northbridge_intel_i440bx_ops = {
 108         .name = "Intel 82443BX (440BX) Northbridge",
 109         .enable_dev = enable_dev,
 110 };