src/northbridge/intel/sandybridge/chip.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H
   4 #define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H
   5
   6 #include <drivers/intel/gma/i915.h>
   7 #include <stdbool.h>
   8 #include <stdint.h>
   9
  10 /*
  11  * Digital Port Hotplug Enable:
  12  *  0x04 = Enabled, 2ms   short pulse
  13  *  0x05 = Enabled, 4.5ms short pulse
  14  *  0x06 = Enabled, 6ms   short pulse
  15  *  0x07 = Enabled, 100ms short pulse
  16  */
  17 struct northbridge_intel_sandybridge_config {
  18         u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
  19         u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
  20         u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
  21
  22         enum {
  23                 PANEL_PORT_LVDS = 0,
  24                 PANEL_PORT_DP_A = 1, /* Also known as eDP */
  25                 PANEL_PORT_DP_C = 2,
  26                 PANEL_PORT_DP_D = 3,
  27         } gpu_panel_port_select;
  28
  29         u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
  30         u16 gpu_panel_power_up_delay;            /* T1+T2 time sequence */
  31         u16 gpu_panel_power_down_delay;          /* T3 time sequence */
  32         u16 gpu_panel_power_backlight_on_delay;  /* T5 time sequence */
  33         u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
  34
  35         u32 gpu_cpu_backlight;  /* CPU Backlight PWM value */
  36         u32 gpu_pch_backlight;  /* PCH Backlight PWM value */
  37
  38         /*
  39          * Maximum memory clock.
  40          * For example 666 for DDR3-1333, or 800 for DDR3-1600
  41          */
  42         u16 max_mem_clock_mhz;
  43
  44         struct i915_gpu_controller_info gfx;
  45
  46         /* Data for RAM init */
  47
  48         /* DIMM SPD address. */
  49         u8 spd_addresses[4];
  50
  51         /* PEI data for RAM init and early silicon init */
  52         u8 ts_addresses[4];
  53
  54         bool ec_present;
  55         bool ddr3lv_support;
  56
  57         /*
  58          * N mode functionality. Leave this setting at 0.
  59          * 0 Auto
  60          * 1 1N
  61          * 2 2N
  62          */
  63         enum {
  64                 DDR_NMODE_AUTO = 0,
  65                 DDR_NMODE_1N,
  66                 DDR_NMODE_2N,
  67         } nmode;
  68
  69         /*
  70          * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to
  71          * specify whether double-rate is required for extended operating temperature range.
  72          *
  73          *   0 Enable double rate based upon temperature thresholds
  74          *   1 Normal rate
  75          *   2 Always enable double rate
  76          */
  77         enum {
  78                 DDR_REFRESH_RATE_TEMP_THRES = 0,
  79                 DDR_REFRESH_REATE_NORMAL,
  80                 DDR_REFRESH_RATE_DOUBLE,
  81         } ddr_refresh_rate_config;
  82
  83         struct {
  84                 /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
  85                 u8 mode                 : 2;
  86                 /*  4 bit mask, 1: switchable, 0: not switchable */
  87                 u8 hs_port_switch_mask  : 4;
  88                 /* 0: No xHCI preOS driver, 1: xHCI preOS driver */
  89                 u8 preboot_support      : 1;
  90                 /* 0: Disable, 1: Enable */
  91                 u8 xhci_streams         : 1;
  92         } usb3;
  93 };
  94
  95 #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */