src/northbridge/intel/sandybridge/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #define __SIMPLE_DEVICE__
   4
   5 #include <arch/romstage.h>
   6 #include <device/pci_ops.h>
   7 #include <cbmem.h>
   8 #include <cpu/intel/smm_reloc.h>
   9 #include <cpu/x86/mtrr.h>
  10 #include <cpu/x86/smm.h>
  11 #include <program_loading.h>
  12 #include "sandybridge.h"
  13 #include <security/intel/txt/txt_platform.h>
  14 #include <stddef.h>
  15 #include <stdint.h>
  16
  17 static uintptr_t northbridge_get_tseg_base(void)
  18 {
  19         /* TSEG has 1 MiB granularity, and bit 0 is a lock */
  20         return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEGMB), 1 * MiB);
  21 }
  22
  23 static size_t northbridge_get_tseg_size(void)
  24 {
  25         return CONFIG_SMM_TSEG_SIZE;
  26 }
  27
  28 union dpr_register txt_get_chipset_dpr(void)
  29 {
  30         return (union dpr_register) { .raw = pci_read_config32(HOST_BRIDGE, DPR) };
  31 }
  32
  33 /*
  34  * Return the topmost memory address below 4 GiB available for general
  35  * use, from software's view of memory. Do not confuse this with TOLUD,
  36  * which applies to the DRAM as viewed by the memory controller itself.
  37  */
  38 static uintptr_t top_of_low_usable_memory(void)
  39 {
  40         /*
  41          * Base of DPR is top of usable DRAM below 4 GiB. However, DPR
  42          * may not always be enabled. Unlike most memory map registers,
  43          * the DPR register stores top of DPR instead of its base address.
  44          * Top of DPR is R/O, and mirrored from TSEG base by hardware.
  45          */
  46         uintptr_t tolum = northbridge_get_tseg_base();
  47
  48         const union dpr_register dpr = txt_get_chipset_dpr();
  49
  50         /* Subtract DMA Protected Range size if enabled */
  51         if (dpr.epm)
  52                 tolum -= dpr.size * MiB;
  53
  54         return tolum;
  55 }
  56
  57 uintptr_t cbmem_top_chipset(void)
  58 {
  59         return top_of_low_usable_memory();
  60 }
  61
  62 void smm_region(uintptr_t *start, size_t *size)
  63 {
  64         *start = northbridge_get_tseg_base();
  65         *size  = northbridge_get_tseg_size();
  66 }
  67
  68 void fill_postcar_frame(struct postcar_frame *pcf)
  69 {
  70         const uintptr_t top_of_ram = cbmem_top();
  71
  72         /*
  73          * Cache 8MiB below the top of ram. On sandybridge systems the top of
  74          * RAM under 4GiB is the start of the TSEG region. It is required to
  75          * be 8MiB aligned. Set this area as cacheable so it can be used later
  76          * for ramstage before setting up the entire RAM as cacheable.
  77          */
  78         postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
  79
  80         /*
  81          * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems
  82          * is where the TSEG region resides. However, it is not restricted
  83          * to SMM mode until SMM has been relocated. By setting the region
  84          * to cacheable it provides faster access when relocating the SMM
  85          * handler as well as using the TSEG region for other purposes.
  86          */
  87         postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK);
  88 }