src/vendorcode/amd/fsp/cezanne/FspUsb.h

   1 #ifndef __FSPUSB_H__
   2 #define __FSPUSB_H__
   3
   4 #include <FspUpd.h>
   5
   6 #define FSP_USB_STRUCT_MAJOR_VERSION    0xd
   7 #define FSP_USB_STRUCT_MINOR_VERSION    0x6
   8
   9 #define USB2_PORT_COUNT 8
  10 #define USB3_PORT_COUNT 4
  11 #define USBC_COMBO_PHY_COUNT 2
  12
  13 struct fch_usb2_phy {
  14         uint8_t                 compdstune;                             ///< COMPDSTUNE
  15         uint8_t                 sqrxtune;                               ///< SQRXTUNE
  16         uint8_t                 txfslstune;                             ///< TXFSLSTUNE
  17         uint8_t                 txpreempamptune;                        ///< TXPREEMPAMPTUNE
  18         uint8_t                 txpreemppulsetune;                      ///< TXPREEMPPULSETUNE
  19         uint8_t                 txrisetune;                             ///< TXRISETUNE
  20         uint8_t                 txvreftune;                             ///< TXVREFTUNE
  21         uint8_t                 txhsxvtune;                             ///< TXHSXVTUNE
  22         uint8_t                 txrestune;                              ///< TXRESTUNE
  23 } __packed;
  24
  25 struct fch_usb3_phy {
  26         uint8_t                 tx_term_ctrl;                           ///< tx_term_ctrl
  27         uint8_t                 rx_term_ctrl;                           ///< rx_term_ctrl
  28         uint8_t                 tx_vboost_lvl_en;                       ///< TX_VBOOST_LVL_EN
  29         uint8_t                 tx_vboost_lvl;                          ///< TX_VBOOST_LVL
  30 } __packed;
  31
  32 #define USB0_PORT0      0
  33 #define USB0_PORT1      1
  34 #define USB0_PORT2      1
  35 #define USB0_PORT3      3
  36 #define USB1_PORT0      (0<<2)
  37 #define USB1_PORT1      (1<<2)
  38 #define USB1_PORT2      (1<<2)
  39 #define USB1_PORT3      (3<<2)
  40
  41 #define USB_COMBO_PHY_MODE_USB_C        0
  42 #define USB_COMBO_PHY_MODE_USB_ONLY     1
  43 #define USB_COMBO_PHY_MODE_USB_DPM      2
  44 #define USB_COMBO_PHY_MODE_USB_DPP      3
  45
  46 struct usb_phy_config {
  47         uint8_t                 Version_Major;                     ///< USB IP version
  48         uint8_t                 Version_Minor;                     ///< USB IP version
  49         uint8_t                 TableLength;                       ///< TableLength
  50         uint8_t                 Reserved0;
  51         struct fch_usb2_phy     Usb2PhyPort[USB2_PORT_COUNT];      ///< USB 2.0 Driving Strength
  52         struct fch_usb3_phy     Usb3PhyPort[USB3_PORT_COUNT];      ///< USB3 PHY Adjustment
  53         uint8_t                 BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
  54         uint8_t                 PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
  55         uint8_t                 ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
  56         uint8_t                 Reserved2[4];
  57 } __packed;
  58
  59 #endif