1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/mmio.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
6 #include <device/pci_ops.h>
11 static DEVTREE_CONST
uint32_t fpga_bar
= CONFIG_EARLY_PCI_MMIO_BASE
;
12 static bool nc_fpga_present
= false;
14 int pci_early_device_probe(u8 bus
, u8 dev
, u32 mmio_base
)
16 pci_devfn_t pci_dev
= PCI_DEV(bus
, dev
, 0);
17 uint32_t id
= pci_s_read_config32(pci_dev
, PCI_VENDOR_ID
);
19 if (id
!= (0x4091 << 16 | PCI_VID_SIEMENS
))
22 /* Setup base address for BAR0. */
23 pci_s_write_config32(pci_dev
, PCI_BASE_ADDRESS_0
, mmio_base
);
24 /* Enable memory access for pci_dev. */
25 u16 reg16
= pci_s_read_config16(pci_dev
, PCI_COMMAND
);
26 reg16
|= PCI_COMMAND_MEMORY
;
27 pci_s_write_config16(pci_dev
, PCI_COMMAND
, reg16
);
28 nc_fpga_present
= true;
33 void nc_fpga_remap(uint32_t new_mmio
)
40 void nc_fpga_post(uint8_t value
)
42 /* The function pci_early_device_probe is called in bootblock and romstage. Make sure
43 that in these stages the initialization code was successful before the POST code
44 value is written to the register. */
45 if ((ENV_BOOTBLOCK
|| ENV_SEPARATE_ROMSTAGE
) && nc_fpga_present
== false)
47 write32p(fpga_bar
+ NC_FPGA_POST_OFFSET
, value
);