src/drivers/uart/oxpcie_early.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdint.h>
   4 #include <device/pci_ops.h>
   5 #include <console/uart.h>
   6 #include <device/pci.h>
   7 #include "uart8250reg.h"
   8
   9 static int oxpcie_present;
  10 static DEVTREE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
  11
  12 int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
  13 {
  14         pci_devfn_t device = PCI_DEV(bus, dev, 0);
  15
  16         u32 id = pci_s_read_config32(device, PCI_VENDOR_ID);
  17         switch (id) {
  18         case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
  19                 /* On this device function 0 is the parallel port, and
  20                  * function 3 is the serial port. So let's go look for
  21                  * the UART.
  22                  */
  23                 device = PCI_DEV(bus, dev, 3);
  24                 id = pci_s_read_config32(device, PCI_VENDOR_ID);
  25                 if (id != 0xc11b1415)
  26                         return -1;
  27                 break;
  28         case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */
  29         case 0xc1581415: /* e.g. Startech MPEX2S952 */
  30                 break;
  31         default:
  32                 /* No UART here. */
  33                 return -1;
  34         }
  35
  36         /* Sanity-check, we assume fixed location. */
  37         if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE)
  38                 return -1;
  39
  40         /* Setup base address on device */
  41         pci_s_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
  42
  43         /* Enable memory on device */
  44         u16 reg16 = pci_s_read_config16(device, PCI_COMMAND);
  45         reg16 |= PCI_COMMAND_MEMORY;
  46         pci_s_write_config16(device, PCI_COMMAND, reg16);
  47
  48         oxpcie_present = 1;
  49         return 0;
  50 }
  51
  52 /*
  53  * Stages that do not call pci_early_device_probe() identify an
  54  * enabled UART with a test read. Since PCI bus enumeration
  55  * has not happened PCI configuration register access is not
  56  * possible here.
  57  */
  58 static int uart_presence(uintptr_t base)
  59 {
  60         /* LCR has no side-effects on reads. */
  61         const u8 reg = UART8250_LCR;
  62         u8 val;
  63
  64         if (CONFIG(DRIVERS_UART_8250MEM_32))
  65                 val = read32p(base + 4 * reg) & 0xff;
  66         else
  67                 val = read8p(base + reg);
  68
  69         if (val == 0xff)
  70                 return -1;
  71
  72         /* Something decoded MMIO read, assume it was the UART. */
  73         return 1;
  74 }
  75
  76 static bool oxpcie_uart_active(void)
  77 {
  78         if (oxpcie_present == 0)
  79                 oxpcie_present = uart_presence(uart0_base);
  80
  81         if (oxpcie_present > 0)
  82                 return true;
  83         if (oxpcie_present < 0)
  84                 return false;
  85
  86         /* not reached */
  87         return false;
  88 }
  89
  90 uintptr_t uart_platform_base(unsigned int idx)
  91 {
  92         if ((idx < 8) && oxpcie_uart_active())
  93                 return uart0_base + idx * 0x200;
  94         return 0;
  95 }
  96
  97 void oxford_remap(u32 new_base)
  98 {
  99 #if ENV_RAMSTAGE
 100         uart0_base = new_base + 0x1000;
 101 #endif
 102 }
 103
 104 unsigned int uart_platform_refclk(void)
 105 {
 106         return 62500000;
 107 }