src/drivers/uart/pl011.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 #ifndef __DRIVERS_UART_PL011_H
   4 #define __DRIVERS_UART_PL011_H
   5
   6 #include <types.h>
   7
   8 /* PL011 r1p5 registers */
   9 struct pl011_uart {
  10         u32 dr;          // offset: 0x0    Data Register
  11         u32 rsr_ecr;     // offset: 0x4    Receive Status Register / Error Clear Register
  12         u8 rsvd1[0x10];  // offset: 0x8    Reserved
  13         u32 fr;          // offset: 0x18   Flag Register
  14         u8 rsvd2[0x4];   // offset: 0x1C   Reserved
  15         u32 ilpr;        // offset: 0x20   (IrDA) Low-Power Counter Register
  16         u32 ibrd;        // offset: 0x24   Integer Baud Rate Register
  17         u32 fbrd;        // offset: 0x28   Fractional Baud Rate Register
  18         u32 lcr_h;       // offset: 0x2C   Line Control Register
  19         u32 cr;          // offset: 0x30   Control Register
  20         u32 ifls;        // offset: 0x34   Interrupt FIFO Level Select Register
  21         u32 imsc;        // offset: 0x38   Interrupt Mask Set/Clear Register
  22         u32 ris;         // offset: 0x3C   Raw Interrupt Status Register
  23         u32 mis;         // offset: 0x40   Masked Interrupt status Register
  24         u32 icr;         // offset: 0x44   Interrupt Clear Register
  25         u32 dmacr;       // offset: 0x48   DMA Control Register
  26         u8 rsvd3[0xf94]; // offset: 0x4C   Reserved
  27         u32 periphid0;   // offset: 0xFE0  UART PeriphID0 Register
  28         u32 periphid1;   // offset: 0xFE4  UART PeriphID1 Register
  29         u32 periphid2;   // offset: 0xFE8  UART PeriphID2 Register
  30         u32 periphid3;   // offset: 0xFEC  UART PeriphID3 Register
  31         u32 cellid0;     // offset: 0xFF0  UART CellID0 Register
  32         u32 cellid1;     // offset: 0xFF4  UART CellID1 Register
  33         u32 cellid2;     // offset: 0xFF8  UART CellID2 Register
  34         u32 cellid3;     // offset: 0xFFC  UART CellID3 Register
  35 };
  36 check_member(pl011_uart, cellid3, 0xffc);
  37
  38 /*************************************************************************/
  39 /* Bit definitions from arm-trusted-firmware/include/drivers/arm/pl011.h */
  40 /*************************************************************************/
  41 /* Flag reg bits */
  42 #define PL011_UARTFR_RI         (1 << 8)        /* Ring indicator */
  43 #define PL011_UARTFR_TXFE       (1 << 7)        /* Transmit FIFO empty */
  44 #define PL011_UARTFR_RXFF       (1 << 6)        /* Receive  FIFO full */
  45 #define PL011_UARTFR_TXFF       (1 << 5)        /* Transmit FIFO full */
  46 #define PL011_UARTFR_RXFE       (1 << 4)        /* Receive FIFO empty */
  47 #define PL011_UARTFR_BUSY       (1 << 3)        /* UART busy */
  48 #define PL011_UARTFR_DCD        (1 << 2)        /* Data carrier detect */
  49 #define PL011_UARTFR_DSR        (1 << 1)        /* Data set ready */
  50 #define PL011_UARTFR_CTS        (1 << 0)        /* Clear to send */
  51
  52 #define PL011_UARTFR_TXFF_BIT   5               /* Transmit FIFO full bit in
  53                                                    UARTFR register */
  54 #define PL011_UARTFR_RXFE_BIT   4               /* Receive FIFO empty bit in
  55                                                    UARTFR register */
  56 #define PL011_UARTFR_BUSY_BIT   3               /* UART busy bit in UARTFR
  57                                                    register */
  58
  59 /* Control reg bits */
  60 #define PL011_UARTCR_CTSEN      (1 << 15)       /* CTS hardware flow control
  61                                                    enable */
  62 #define PL011_UARTCR_RTSEN      (1 << 14)       /* RTS hardware flow control
  63                                                    enable */
  64 #define PL011_UARTCR_RTS        (1 << 11)       /* Request to send */
  65 #define PL011_UARTCR_DTR        (1 << 10)       /* Data transmit ready. */
  66 #define PL011_UARTCR_RXE        (1 << 9)        /* Receive enable */
  67 #define PL011_UARTCR_TXE        (1 << 8)        /* Transmit enable */
  68 #define PL011_UARTCR_LBE        (1 << 7)        /* Loopback enable */
  69 #define PL011_UARTCR_UARTEN     (1 << 0)        /* UART Enable */
  70
  71 /* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */
  72 #define PL011_LINE_CONTROL      (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8)
  73
  74 /* Line Control Register Bits */
  75 #define PL011_UARTLCR_H_SPS     (1 << 7)        /* Stick parity select */
  76 #define PL011_UARTLCR_H_WLEN_8  (3 << 5)
  77 #define PL011_UARTLCR_H_WLEN_7  (2 << 5)
  78 #define PL011_UARTLCR_H_WLEN_6  (1 << 5)
  79 #define PL011_UARTLCR_H_WLEN_5  (0 << 5)
  80 #define PL011_UARTLCR_H_FEN     (1 << 4)        /* FIFOs Enable */
  81 #define PL011_UARTLCR_H_STP2    (1 << 3)        /* Two stop bits select */
  82 #define PL011_UARTLCR_H_EPS     (1 << 2)        /* Even parity select */
  83 #define PL011_UARTLCR_H_PEN     (1 << 1)        /* Parity Enable */
  84 #define PL011_UARTLCR_H_BRK     (1 << 0)        /* Send break */
  85
  86 #endif                          /* ! __DRIVERS_UART_PL011_H */