1 /* SPDX-License-Identifier: GPL-2.0-only */
4 #include <boot/coreboot_tables.h>
5 #include <commonlib/bsd/helpers.h>
6 #include <console/uart.h>
9 #include "uart8250reg.h"
11 /* Should support 8250, 16450, 16550, 16550A type UARTs */
13 /* Expected character delay at 1200bps is 9ms for a working UART
14 * and no flow-control. Assume UART as stuck if shift register
15 * or FIFO takes more than 50ms per character to appear empty.
17 * Estimated that inb() from UART takes 1 microsecond.
19 #define SINGLE_CHAR_TIMEOUT (50 * 1000)
20 #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
22 static int uart8250_can_tx_byte(unsigned int base_port
)
24 return inb(base_port
+ UART8250_LSR
) & UART8250_LSR_THRE
;
27 static void uart8250_tx_byte(unsigned int base_port
, unsigned char data
)
29 unsigned long int i
= SINGLE_CHAR_TIMEOUT
;
30 while (i
-- && !uart8250_can_tx_byte(base_port
));
31 outb(data
, base_port
+ UART8250_TBR
);
34 static void uart8250_tx_flush(unsigned int base_port
)
36 unsigned long int i
= FIFO_TIMEOUT
;
37 while (i
-- && !(inb(base_port
+ UART8250_LSR
) & UART8250_LSR_TEMT
));
40 static int uart8250_can_rx_byte(unsigned int base_port
)
42 return inb(base_port
+ UART8250_LSR
) & UART8250_LSR_DR
;
45 static unsigned char uart8250_rx_byte(unsigned int base_port
)
47 unsigned long int i
= SINGLE_CHAR_TIMEOUT
;
48 while (i
&& !uart8250_can_rx_byte(base_port
))
52 return inb(base_port
+ UART8250_RBR
);
57 static void uart8250_init(unsigned int base_port
, unsigned int divisor
)
59 /* Disable interrupts */
60 outb(0x0, base_port
+ UART8250_IER
);
62 outb(UART8250_FCR_FIFO_EN
, base_port
+ UART8250_FCR
);
64 /* assert DTR and RTS so the other end is happy */
65 outb(UART8250_MCR_DTR
| UART8250_MCR_RTS
, base_port
+ UART8250_MCR
);
68 outb(UART8250_LCR_DLAB
| CONFIG_TTYS0_LCS
, base_port
+ UART8250_LCR
);
70 /* Set Baud Rate Divisor. 12 ==> 9600 Baud */
71 outb(divisor
& 0xFF, base_port
+ UART8250_DLL
);
72 outb((divisor
>> 8) & 0xFF, base_port
+ UART8250_DLM
);
74 /* Set to 3 for 8N1 */
75 outb(CONFIG_TTYS0_LCS
, base_port
+ UART8250_LCR
);
78 static const unsigned int bases
[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
80 uintptr_t uart_platform_base(unsigned int idx
)
82 if (idx
< ARRAY_SIZE(bases
))
87 void uart_init(unsigned int idx
)
89 if (!CONFIG(DRIVERS_UART_8250IO_SKIP_INIT
)) {
91 div
= uart_baudrate_divisor(get_uart_baudrate(),
92 uart_platform_refclk(), uart_input_clock_divider());
93 uart8250_init(uart_platform_base(idx
), div
);
97 void uart_tx_byte(unsigned int idx
, unsigned char data
)
99 uart8250_tx_byte(uart_platform_base(idx
), data
);
102 unsigned char uart_rx_byte(unsigned int idx
)
104 return uart8250_rx_byte(uart_platform_base(idx
));
107 void uart_tx_flush(unsigned int idx
)
109 uart8250_tx_flush(uart_platform_base(idx
));
112 enum cb_err
fill_lb_serial(struct lb_serial
*serial
)
114 serial
->type
= LB_SERIAL_TYPE_IO_MAPPED
;
115 serial
->baseaddr
= uart_platform_base(CONFIG_UART_FOR_CONSOLE
);
116 serial
->baud
= get_uart_baudrate();
117 serial
->regwidth
= 1;
118 serial
->input_hertz
= uart_platform_refclk();