src/southbridge/intel/bd82x6x/early_rcba.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include "pch.h"
   4
   5 void southbridge_configure_default_intmap(void)
   6 {
   7         /*
   8          * For the PCH internal PCI functions, provide a reasonable
   9          * default IRQ mapping that utilizes only PIRQ A to D. Higher
  10          * PIRQs are sometimes used for other on-board chips that
  11          * require an edge triggered interrupt which is not shareable.
  12          */
  13
  14         /*
  15          * We use a linear mapping for the pin numbers. They are not
  16          * physical pins, and thus, have no relation between the dif-
  17          * ferent devices. Only rule we must obey is that a single-
  18          * function device has to use pin A.
  19          */
  20         RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) |
  21                         (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
  22         RCBA32(D29IP) = (INTA << D29IP_E1P);
  23         RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) |
  24                         (INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) |
  25                         (INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) |
  26                         (INTB << D28IP_P2IP) | (INTA << D28IP_P1IP);
  27         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  28         RCBA32(D26IP) = (INTA << D26IP_E2P);
  29         RCBA32(D25IP) = (INTA << D25IP_LIP);
  30         RCBA32(D22IP) = (INTA << D22IP_MEI1IP);
  31         RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
  32
  33         /*
  34          * For the PIRQ allocation the following was taken into
  35          * account:
  36          *   o Interrupts of the PCIe root ports are only about
  37          *     events at the ports, not downstream devices. So we
  38          *     don't expect many interrupts there and ignore them.
  39          *   o We don't expect to talk constantly to the ME either
  40          *     so ignore that, too. Same for SMBus and the thermal
  41          *     device.
  42          *   o Second SATA interface is only used in non-AHCI mode
  43          *     so unlikely to coexist with modern interfaces (e.g.
  44          *     xHCI).
  45          *   o An OS that knows USB3 will likely also know how to
  46          *     use MSI.
  47          *
  48          * The functions that might matter first:
  49          *
  50          * D31IP_SIP    SATA 1  -> PIRQ A (MSI capable in AHCI mode)
  51          * D31IP_SIP2   SATA 2  -> PIRQ B
  52          * D29IP_E1P    EHCI 1  -> PIRQ C
  53          * D27IP_ZIP    HDA     -> PIRQ D (MSI capable)
  54          * D26IP_E2P    EHCI 2  -> PIRQ D
  55          * D25IP_LIP    GbE     -> PIRQ B (MSI capable)
  56          * D20IP_XHCIIP xHCI    -> PIRQ B (MSI capable)
  57          *
  58          * D31IP_TTIP   Thermal -> PIRQ B
  59          * D31IP_SMIP   SMBUS   -> PIRQ A
  60          * D28IP_*      PCIe RP -> PIRQ A-D (MSI capable)
  61          * D22IP_MEI1IP ME      -> PIRQ A (MSI capable)
  62          *
  63          * Note, CPU-integrated functions seem to always use PIRQ A.
  64          */
  65 #define _none 0
  66         DIR_ROUTE(D31IR, PIRQA, PIRQA, PIRQB, PIRQB);
  67         DIR_ROUTE(D29IR, PIRQC, _none, _none, _none);
  68         DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD);
  69         DIR_ROUTE(D27IR, PIRQD, _none, _none, _none);
  70         DIR_ROUTE(D26IR, PIRQD, _none, _none, _none);
  71         DIR_ROUTE(D25IR, PIRQB, _none, _none, _none);
  72         DIR_ROUTE(D22IR, PIRQA, _none, _none, _none);
  73         DIR_ROUTE(D20IR, PIRQB, _none, _none, _none);
  74 #undef _none
  75
  76         /* Enable IOAPIC (generic) */
  77         RCBA16(OIC) = 0x0100;
  78         /* PCH BWG says to read back the IOAPIC enable register */
  79         (void)RCBA16(OIC);
  80 }
  81
  82 void southbridge_rcba_config(void)
  83 {
  84         RCBA32(FD) = PCH_DISABLE_ALWAYS;
  85 }