src/southbridge/intel/bd82x6x/pci.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ops.h>
   7 #include <device/pci_ids.h>
   8 #include "pch.h"
   9
  10 static void pci_init(struct device *dev)
  11 {
  12         u16 reg16;
  13
  14         printk(BIOS_DEBUG, "PCI init.\n");
  15         /* Enable Bus Master */
  16         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
  17
  18         /* This device has no interrupt */
  19         pci_write_config8(dev, INTR, 0xff);
  20
  21         /* disable parity error response and SERR */
  22         pci_and_config16(dev, PCI_BRIDGE_CONTROL,
  23                          ~(PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR));
  24
  25         /* Master Latency Count must be set to 0x04! */
  26         pci_update_config8(dev, SMLT, 0x07, (0x04 << 3));
  27
  28         /* Clear errors in status registers. FIXME: do we need to do something? */
  29         reg16 = pci_read_config16(dev, PSTS);
  30         //reg16 |= 0xf900;
  31         pci_write_config16(dev, PSTS, reg16);
  32
  33         reg16 = pci_read_config16(dev, SECSTS);
  34         // reg16 |= 0xf900;
  35         pci_write_config16(dev, SECSTS, reg16);
  36 }
  37
  38 struct device_operations bd82x6x_pci_bridge_ops = {
  39         .read_resources         = pci_bus_read_resources,
  40         .set_resources          = pci_dev_set_resources,
  41         .enable_resources       = pci_bus_enable_resources,
  42         .init                   = pci_init,
  43         .scan_bus               = pci_scan_bridge,
  44         .ops_pci                = &pci_dev_ops_pci,
  45 };