src/southbridge/intel/bd82x6x/sata.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <option.h>
  10 #include <acpi/acpi_sata.h>
  11 #include <types.h>
  12
  13 #include "chip.h"
  14 #include "pch.h"
  15
  16 typedef struct southbridge_intel_bd82x6x_config config_t;
  17
  18 static inline u32 sir_read(struct device *dev, int idx)
  19 {
  20         pci_write_config32(dev, SATA_SIRI, idx);
  21         return pci_read_config32(dev, SATA_SIRD);
  22 }
  23
  24 static inline void sir_write(struct device *dev, int idx, u32 value)
  25 {
  26         pci_write_config32(dev, SATA_SIRI, idx);
  27         pci_write_config32(dev, SATA_SIRD, value);
  28 }
  29
  30 static void sata_read_resources(struct device *dev)
  31 {
  32         struct resource *res;
  33
  34         pci_dev_read_resources(dev);
  35
  36         /* Assign fixed resources for IDE legacy mode */
  37
  38         u8 sata_mode = get_uint_option("sata_mode", 0);
  39         if (sata_mode != 2)
  40                 return;
  41
  42         res = probe_resource(dev, PCI_BASE_ADDRESS_0);
  43         if (res) {
  44                 res->base = 0x1f0;
  45                 res->size = 8;
  46                 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  47         }
  48
  49         res = probe_resource(dev, PCI_BASE_ADDRESS_1);
  50         if (res) {
  51                 res->base = 0x3f4;
  52                 res->size = 4;
  53                 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  54         }
  55
  56         res = probe_resource(dev, PCI_BASE_ADDRESS_2);
  57         if (res) {
  58                 res->base = 0x170;
  59                 res->size = 8;
  60                 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  61         }
  62
  63         res = probe_resource(dev, PCI_BASE_ADDRESS_3);
  64         if (res) {
  65                 res->base = 0x374;
  66                 res->size = 4;
  67                 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  68         }
  69 }
  70
  71 static void sata_set_resources(struct device *dev)
  72 {
  73         /* work around bug in pci_dev_set_resources(), it bails out on FIXED */
  74         u8 sata_mode = get_uint_option("sata_mode", 0);
  75         if (sata_mode == 2) {
  76                 unsigned int i;
  77                 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) {
  78                         struct resource *const res = probe_resource(dev, i);
  79                         if (res)
  80                                 res->flags &= ~IORESOURCE_FIXED;
  81                 }
  82         }
  83
  84         pci_dev_set_resources(dev);
  85 }
  86
  87 static void sata_init(struct device *dev)
  88 {
  89         u32 reg32;
  90         u16 reg16;
  91         /* Get the chip configuration */
  92         config_t *config = dev->chip_info;
  93
  94         printk(BIOS_DEBUG, "SATA: Initializing...\n");
  95
  96         if (config == NULL) {
  97                 printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
  98                 return;
  99         }
 100
 101         /* Default to AHCI */
 102         u8 sata_mode = get_uint_option("sata_mode", 0);
 103
 104         /* SATA configuration */
 105
 106         /* Enable BARs */
 107         pci_write_config16(dev, PCI_COMMAND,
 108                            PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 109
 110         /* AHCI */
 111         if (sata_mode == 0) {
 112                 u8 *abar;
 113
 114                 printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
 115
 116                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
 117                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
 118
 119                 /* for AHCI, Port Enable is managed in memory mapped space */
 120                 reg16 = pci_read_config16(dev, 0x92);
 121                 reg16 &= ~0x3f; /* 6 ports SKU + ORM */
 122                 reg16 |= 0x8000 | config->sata_port_map;
 123                 pci_write_config16(dev, 0x92, reg16);
 124
 125                 /* SATA Initialization register */
 126                 pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
 127
 128                 /* Initialize AHCI memory-mapped space */
 129                 abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 130                 printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 131                 /* CAP (HBA Capabilities) : enable power management */
 132                 reg32 = read32(abar + 0x00);
 133                 reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
 134                 reg32 &= ~0x00020060; // clear SXS+EMS+PMS
 135                 /* Set ISS, if available */
 136                 if (config->sata_interface_speed_support)
 137                 {
 138                         reg32 &= ~0x00f00000;
 139                         reg32 |= (config->sata_interface_speed_support & 0x03)
 140                           << 20;
 141                 }
 142                 write32(abar + 0x00, reg32);
 143                 /* PI (Ports implemented) */
 144                 write32(abar + 0x0c, config->sata_port_map);
 145                 (void)read32(abar + 0x0c); /* Read back 1 */
 146                 (void)read32(abar + 0x0c); /* Read back 2 */
 147                 /* CAP2 (HBA Capabilities Extended)*/
 148                 reg32 = read32(abar + 0x24);
 149                 reg32 &= ~0x00000002;
 150                 write32(abar + 0x24, reg32);
 151                 /* VSP (Vendor Specific Register */
 152                 reg32 = read32(abar + 0xa0);
 153                 reg32 &= ~0x00000005;
 154                 write32(abar + 0xa0, reg32);
 155         } else {
 156                 /* IDE */
 157
 158                 /* Without AHCI BAR no memory decoding */
 159                 pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
 160
 161                 if (sata_mode == 1) {
 162                         /* Native mode on both primary and secondary. */
 163                         pci_or_config8(dev, 0x09, 0x05);
 164                         printk(BIOS_DEBUG, "SATA: Controller in IDE compat mode.\n");
 165                 } else {
 166                         /* Legacy mode on both primary and secondary. */
 167                         pci_and_config8(dev, 0x09, ~0x05);
 168                         printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n");
 169                 }
 170
 171                 /* Enable I/O decoding */
 172                 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
 173                 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
 174
 175                 /* Port enable + OOB retry mode */
 176                 pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map | 0x8000);
 177
 178                 /* SATA Initialization register */
 179                 pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
 180         }
 181
 182         /* Set Gen3 Transmitter settings if needed */
 183         if (config->sata_port0_gen3_tx)
 184                 pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
 185                                 config->sata_port0_gen3_tx);
 186
 187         if (config->sata_port1_gen3_tx)
 188                 pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
 189                                 config->sata_port1_gen3_tx);
 190
 191         /* Additional Programming Requirements */
 192         sir_write(dev, 0x04, 0x00001600);
 193         sir_write(dev, 0x28, 0xa0000033);
 194         reg32 = sir_read(dev, 0x54);
 195         reg32 &= 0xff000000;
 196         reg32 |= 0x5555aa;
 197         sir_write(dev, 0x54, reg32);
 198         sir_write(dev, 0x64, 0xcccc8484);
 199         reg32 = sir_read(dev, 0x68);
 200         reg32 &= 0xffff0000;
 201         reg32 |= 0xcccc;
 202         sir_write(dev, 0x68, reg32);
 203         reg32 = sir_read(dev, 0x78);
 204         reg32 &= 0x0000ffff;
 205         reg32 |= 0x88880000;
 206         sir_write(dev, 0x78, reg32);
 207         sir_write(dev, 0x84, 0x001c7000);
 208         sir_write(dev, 0x88, 0x88338822);
 209         sir_write(dev, 0xa0, 0x001c7000);
 210         // a4
 211         sir_write(dev, 0xc4, 0x0c0c0c0c);
 212         sir_write(dev, 0xc8, 0x0c0c0c0c);
 213         sir_write(dev, 0xd4, 0x10000000);
 214
 215         pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
 216         pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
 217
 218         pci_update_config32(dev, 0x98,
 219                 ~(1 << 16 | 0x3f << 7 | 3 << 5 | 3 << 3),
 220                 1 << 24 | 1 << 22 | 1 << 20 | 1 << 19 |
 221                 1 << 18 | 1 << 14 | 0x04 << 7 | 1 << 3);
 222
 223         /* SATA clock gating. Must be done after writing register 0x94. */
 224         pch_iobp_update(0xEA007F07, ~0U, (1 << 31));
 225         pch_iobp_update(0xEA004000, ~0U, (1 << 7));
 226 }
 227
 228 static void sata_enable(struct device *dev)
 229 {
 230         /* Get the chip configuration */
 231         config_t *config = dev->chip_info;
 232         u16 map = 0;
 233
 234         if (!config)
 235                 return;
 236
 237         u8 sata_mode = get_uint_option("sata_mode", 0);
 238
 239         /*
 240          * Set SATA controller mode early so the resource allocator can
 241          * properly assign IO/Memory resources for the controller.
 242          */
 243         if (sata_mode == 0)
 244                 map = 0x0060;
 245
 246         map |= (config->sata_port_map ^ 0x3f) << 8;
 247
 248         pci_write_config16(dev, 0x90, map);
 249 }
 250
 251 static const char *sata_acpi_name(const struct device *dev)
 252 {
 253         return "SATA";
 254 }
 255
 256 static void sata_fill_ssdt(const struct device *dev)
 257 {
 258         config_t *config = dev->chip_info;
 259         generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
 260 }
 261
 262 static struct device_operations sata_ops = {
 263         .read_resources         = sata_read_resources,
 264         .set_resources          = sata_set_resources,
 265         .enable_resources       = pci_dev_enable_resources,
 266         .acpi_fill_ssdt         = sata_fill_ssdt,
 267         .init                   = sata_init,
 268         .enable                 = sata_enable,
 269         .ops_pci                = &pci_dev_ops_pci,
 270         .acpi_name              = sata_acpi_name,
 271 };
 272
 273 static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
 274                                                  0x1e00, 0x1e01, 0x1e02, 0x1e03,
 275                                                  0 };
 276
 277 static const struct pci_driver pch_sata __pci_driver = {
 278         .ops     = &sata_ops,
 279         .vendor  = PCI_VID_INTEL,
 280         .devices = pci_device_ids,
 281 };