src/southbridge/intel/i82801jx/acpi/ich10.asl

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /* Intel 82801Ix support */
   4
   5 #include "../i82801jx.h"
   6
   7 Scope(\)
   8 {
   9         // ICH10 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
  10         OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
  11         Field(PMIO, ByteAcc, NoLock, Preserve)
  12         {
  13                 Offset(0x11),
  14                 THRO, 1,        // force thermal throttling
  15                 Offset(0x42),   // General Purpose Control
  16                 , 1,            // skip 1 bit
  17                 GPEC, 1,        // TCO status
  18                 Offset(0x64),
  19                 , 9,            // skip 9 more bits
  20                 SCIS, 1         // TCO DMI status
  21         }
  22
  23         // ICH10 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
  24         OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
  25         Field(GPIO, ByteAcc, NoLock, Preserve)
  26         {
  27                                 // GPIO Use Select
  28                 GU00, 8,
  29                 GU01, 8,
  30                 GU02, 8,
  31                 GU03, 8,
  32                 Offset(0x04),   // GPIO IO Select
  33                 GIO0, 8,
  34                 GIO1, 8,
  35                 GIO2, 8,
  36                 GIO3, 8,
  37                 Offset(0x0c),   // GPIO Level
  38                 GP00, 1,
  39                 GP01, 1,
  40                 GP02, 1,
  41                 GP03, 1,
  42                 GP04, 1,
  43                 GP05, 1,
  44                 GP06, 1,
  45                 GP07, 1,
  46                 GP08, 1,
  47                 GP09, 1,
  48                 GP10, 1,
  49                 GP11, 1,
  50                 GP12, 1,
  51                 GP13, 1,
  52                 GP14, 1,
  53                 GP15, 1,
  54                 GP16, 1,
  55                 GP17, 1,
  56                 GP18, 1,
  57                 GP19, 1,
  58                 GP20, 1,
  59                 GP21, 1,
  60                 GP22, 1,
  61                 GP23, 1,
  62                 GP24, 1,
  63                 GP25, 1,
  64                 GP26, 1,
  65                 GP27, 1,
  66                 GP28, 1,
  67                 GP29, 1,
  68                 GP30, 1,
  69                 GP31, 1,
  70                 Offset(0x18),   // GPIO Blink
  71                 GB00, 8,
  72                 GB01, 8,
  73                 GB02, 8,
  74                 GB03, 8,
  75                 Offset(0x2c),   // GPIO Invert
  76                 GIV0, 8,
  77                 GIV1, 8,
  78                 GIV2, 8,
  79                 GIV3, 8,
  80                 Offset(0x30),   // GPIO Use Select 2
  81                 GU04, 8,
  82                 GU05, 8,
  83                 GU06, 8,
  84                 GU07, 8,
  85                 Offset(0x34),   // GPIO IO Select 2
  86                 GIO4, 8,
  87                 GIO5, 8,
  88                 GIO6, 8,
  89                 GIO7, 8,
  90                 Offset(0x38),   // GPIO Level 2
  91                 GP32, 1,
  92                 GP33, 1,
  93                 GP34, 1,
  94                 GP35, 1,
  95                 GP36, 1,
  96                 GP37, 1,
  97                 GP38, 1,
  98                 GP39, 1,
  99                 GL05, 8,
 100                 GL06, 8,
 101                 GL07, 8
 102         }
 103
 104
 105         // ICH10 Root Complex Register Block. Memory Mapped through RCBA)
 106         OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
 107         Field(RCRB, DWordAcc, Lock, Preserve)
 108         {
 109                 Offset(0x0000), // Backbone
 110                 Offset(0x1000), // Chipset
 111                 Offset(0x3000), // Legacy Configuration Registers
 112                 Offset(0x3404), // High Performance Timer Configuration
 113                 HPAS, 2,        // Address Select
 114                 , 5,
 115                 HPTE, 1,        // Address Enable
 116                 Offset(0x3418), // FD (Function Disable)
 117                 , 2,            // Reserved
 118                 SA1D, 1,        // SATA disable
 119                 SMBD, 1,        // SMBUS disable
 120                 HDAD, 1,        // Azalia disable
 121                 , 2,            // Reserved
 122                 US6D, 1,        // UHCI #6 disable
 123                 US1D, 1,        // UHCI #1 disable
 124                 US2D, 1,        // UHCI #2 disable
 125                 US3D, 1,        // UHCI #3 disable
 126                 US4D, 1,        // UHCI #4 disable
 127                 US5D, 1,        // UHCI #5 disable
 128                 EH2D, 1,        // EHCI disable
 129                 LPBD, 1,        // LPC bridge disable
 130                 EH1D, 1,        // EHCI disable
 131                 Offset(0x341a), // FD Root Ports
 132                 RP1D, 1,        // Root Port 1 disable
 133                 RP2D, 1,        // Root Port 2 disable
 134                 RP3D, 1,        // Root Port 3 disable
 135                 RP4D, 1,        // Root Port 4 disable
 136                 RP5D, 1,        // Root Port 5 disable
 137                 RP6D, 1,        // Root Port 6 disable
 138                 , 2,            // Reserved
 139                 THRD, 1,        // Thermal Throttle disable
 140                 SA2D, 1,        // SATA disable
 141         }
 142
 143 }
 144
 145 // 0:1b.0 High Definition Audio (Azalia)
 146 #include <southbridge/intel/common/acpi/audio_ich.asl>
 147
 148 // PCI Express Ports
 149 #include <southbridge/intel/common/acpi/pcie.asl>
 150
 151 // USB
 152 #include "usb.asl"
 153
 154 // PCI Bridge
 155 #include "pci.asl"
 156
 157 // LPC Bridge
 158 #include "lpc.asl"
 159
 160 // SATA
 161 #include "sata.asl"
 162
 163 // SMBus
 164 #include <southbridge/intel/common/acpi/smbus.asl>
 165
 166 Method (_OSC, 4)
 167 {
 168         /* Check for proper GUID */
 169         If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
 170         {
 171                 /* Let OS control everything */
 172                 Return (Arg3)
 173         }
 174         Else
 175         {
 176                 /* Unrecognized UUID */
 177                 CreateDWordField (Arg3, 0, CDW1)
 178                 CDW1 |= 4
 179                 Return (Arg3)
 180         }
 181 }