src/southbridge/intel/i82801jx/sata.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/io.h>
   4 #include <device/mmio.h>
   5 #include <device/pci_ops.h>
   6 #include <console/console.h>
   7 #include <device/device.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <option.h>
  11 #include <types.h>
  12
  13 #include "chip.h"
  14 #include "i82801jx.h"
  15
  16 typedef struct southbridge_intel_i82801jx_config config_t;
  17
  18 static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map)
  19 {
  20         int i;
  21         u32 reg32;
  22         struct resource *res;
  23
  24         /* Initialize AHCI memory-mapped space */
  25         res = probe_resource(dev, PCI_BASE_ADDRESS_5);
  26         if (!res)
  27                 return;
  28
  29         u8 *abar = res2mmio(res, 0, 0);
  30         printk(BIOS_DEBUG, "ABAR: %p\n", abar);
  31
  32         /* Set AHCI access mode.
  33            No other ABAR registers should be accessed before this. */
  34         reg32 = read32(abar + 0x04);
  35         reg32 |= 1 << 31;
  36         write32(abar + 0x04, reg32);
  37
  38         /* CAP (HBA Capabilities) : enable power management */
  39         reg32 = read32(abar + 0x00);
  40         /* CCCS must be set. */
  41         reg32 |= 0x0c006080;  /* set CCCS+PSC+SSC+SALP+SSS */
  42         reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
  43         write32(abar + 0x00, reg32);
  44
  45         /* PI (Ports implemented) */
  46         write32(abar + 0x0c, port_map);
  47         /* PCH code reads back twice, do we need it, too? */
  48         (void)read32(abar + 0x0c); /* Read back 1 */
  49         (void)read32(abar + 0x0c); /* Read back 2 */
  50
  51         /* VSP (Vendor Specific Register) */
  52         reg32 = read32(abar + 0xa0);
  53         reg32 &= ~0x00000001; /* clear SLPD */
  54         write32(abar + 0xa0, reg32);
  55
  56         /* Lock R/WO bits in Port command registers. */
  57         for (i = 0; i < 6; ++i) {
  58                 u8 *addr = abar + 0x118 + (i * 0x80);
  59                 write32(addr, read32(addr));
  60         }
  61 }
  62
  63 static void sata_program_indexed(struct device *const dev)
  64 {
  65         u32 reg32;
  66
  67         pci_write_config8(dev, D31F2_SIDX, 0x18);
  68         reg32 = pci_read_config32(dev, D31F2_SDAT);
  69         reg32 &= ~((7 << 6) | (7 << 3) | (7 << 0));
  70         reg32 |= (3 << 3) | (3 << 0);
  71         pci_write_config32(dev, D31F2_SDAT, reg32);
  72
  73         pci_write_config8(dev, D31F2_SIDX, 0x28);
  74         pci_write_config32(dev, D31F2_SDAT, 0x00cc2080);
  75
  76         pci_write_config8(dev, D31F2_SIDX, 0x40);
  77         pci_write_config8(dev, D31F2_SDAT + 2, 0x22);
  78
  79         pci_write_config8(dev, D31F2_SIDX, 0x78);
  80         pci_write_config8(dev, D31F2_SDAT + 2, 0x22);
  81
  82         pci_write_config8(dev, D31F2_SIDX, 0x84);
  83         reg32 = pci_read_config32(dev, D31F2_SDAT);
  84         reg32 &= ~((7 << 3) | (7 << 0));
  85         reg32 |= (3 << 3) | (3 << 0);
  86         pci_write_config32(dev, D31F2_SDAT, reg32);
  87
  88         pci_write_config8(dev, D31F2_SIDX, 0x88);
  89         reg32 = pci_read_config32(dev, D31F2_SDAT);
  90         reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8));
  91         reg32 &= ~((7 << 19) | (7 << 16) | (7 <<  3) | (7 << 0));
  92         reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8);
  93         reg32 |= (4 << 19) | (4 << 16) | (2 <<  3) | (2 << 0);
  94         pci_write_config32(dev, D31F2_SDAT, reg32);
  95
  96         pci_write_config8(dev, D31F2_SIDX, 0x8c);
  97         reg32 = pci_read_config32(dev, D31F2_SDAT);
  98         reg32 &= ~((7 << 27) | (7 << 24));
  99         reg32 &= ~((7 << 19) | (7 << 16) | 0xffff);
 100         reg32 |= (2 << 27) | (2 << 24);
 101         reg32 |= (2 << 19) | (2 << 16) | 0x00aa;
 102         pci_write_config32(dev, D31F2_SDAT, reg32);
 103
 104         pci_write_config8(dev, D31F2_SIDX, 0x94);
 105         pci_write_config32(dev, D31F2_SDAT, 0x00000022);
 106
 107         pci_write_config8(dev, D31F2_SIDX, 0xa0);
 108         reg32 = pci_read_config32(dev, D31F2_SDAT);
 109         reg32 &= ~((7 << 3) | (7 << 0));
 110         reg32 |= (3 << 3) | (3 << 0);
 111         pci_write_config32(dev, D31F2_SDAT, reg32);
 112
 113         pci_write_config8(dev, D31F2_SIDX, 0xa8);
 114         reg32 = pci_read_config32(dev, D31F2_SDAT);
 115         reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0));
 116         reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0);
 117         pci_write_config32(dev, D31F2_SDAT, reg32);
 118
 119         pci_write_config8(dev, D31F2_SIDX, 0xac);
 120         reg32 = pci_read_config32(dev, D31F2_SDAT);
 121         reg32 &= ~((7 << 19) | (7 << 16) | 0xffff);
 122         reg32 |= (2 << 19) | (2 << 16) | 0x000a;
 123         pci_write_config32(dev, D31F2_SDAT, reg32);
 124 }
 125
 126 static void sata_init(struct device *const dev)
 127 {
 128         u16 reg16;
 129
 130         /* Get the chip configuration */
 131         const config_t *const config = dev->chip_info;
 132
 133         printk(BIOS_DEBUG, "i82801jx_sata: initializing...\n");
 134
 135         if (config == NULL) {
 136                 printk(BIOS_ERR, "i82801jx_sata: error: "
 137                                  "device not in devicetree.cb!\n");
 138                 return;
 139         }
 140
 141         /* Default to AHCI */
 142         u8 sata_mode = get_uint_option("sata_mode", 0);
 143
 144         /*
 145          * TODO: In contrast to ICH7 and PCH code we don't set
 146          * timings, dma and IDE-I/O settings here. Looks like they
 147          * became obsolete with the fading of real IDE ports.
 148          * Maybe we can safely remove those settings from PCH code and
 149          * even ICH7 code if it doesn't use the feature to combine the
 150          * IDE and SATA controllers.
 151          */
 152
 153         pci_write_config16(dev, PCI_COMMAND,
 154                         PCI_COMMAND_MASTER |
 155                         PCI_COMMAND_MEMORY | /* read-only in IDE modes */
 156                         PCI_COMMAND_IO);
 157         if (sata_mode != 0)
 158                 /* No AHCI: clear AHCI base */
 159                 pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
 160
 161         if (sata_mode == 0) {
 162                 printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
 163         } else {
 164                 printk(BIOS_DEBUG, "SATA controller in native mode.\n");
 165
 166                 /* Enable native mode on both primary and secondary. */
 167                 pci_write_config8(dev, PCI_CLASS_PROG, 0x8f);
 168         }
 169
 170         /* Looks like we should only enable decoding here. */
 171         pci_write_config16(dev, D31F2_IDE_TIM_PRI, (1 << 15));
 172         pci_write_config16(dev, D31F2_IDE_TIM_SEC, (1 << 15));
 173
 174         /* Port enable. For AHCI, it's managed in memory mapped space. */
 175         reg16 = pci_read_config16(dev, 0x92);
 176         reg16 &= ~0x3f;
 177         reg16 |= (1 << 15) | ((sata_mode == 0) ? 0x3f : config->sata_port_map);
 178         pci_write_config16(dev, 0x92, reg16);
 179
 180         /* SATA clock settings */
 181         u32 sclkcg = 0;
 182         if (config->sata_clock_request &&
 183                         !(inb(DEFAULT_GPIOBASE + 0x30) & (1 << (35 - 32))))
 184                 sclkcg |= 1 << 30; /* Enable SATA clock request. */
 185         /* Disable unused ports. */
 186         sclkcg |= ((~config->sata_port_map) & 0x3f) << 24;
 187         /* Must be programmed. */
 188         sclkcg |= 0x193;
 189         pci_write_config32(dev, 0x94, sclkcg);
 190
 191         if (sata_mode == 0)
 192                 sata_enable_ahci_mmap(dev, config->sata_port_map);
 193
 194         sata_program_indexed(dev);
 195 }
 196
 197 static void sata_enable(struct device *dev)
 198 {
 199         /* Get the chip configuration */
 200         const config_t *const config = dev->chip_info;
 201
 202         u16 map = 0;
 203
 204         if (!config)
 205                 return;
 206
 207         /* Default to AHCI */
 208         u8 sata_mode = get_uint_option("sata_mode", 0);
 209
 210         /*
 211          * Set SATA controller mode early so the resource allocator can
 212          * properly assign IO/Memory resources for the controller.
 213          */
 214         if (sata_mode == 0)
 215                 map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */
 216
 217         map |= (config->sata_port_map ^ 0x3f) << 8;
 218
 219         pci_write_config16(dev, 0x90, map);
 220 }
 221
 222 static struct device_operations sata_ops = {
 223         .read_resources         = pci_dev_read_resources,
 224         .set_resources          = pci_dev_set_resources,
 225         .enable_resources       = pci_dev_enable_resources,
 226         .init                   = sata_init,
 227         .enable                 = sata_enable,
 228         .ops_pci                = &pci_dev_ops_pci,
 229 };
 230
 231 static const unsigned short pci_device_ids[] = {
 232         0x3a00,
 233         0x3a02,
 234         0x3a05,
 235         0x3a06,
 236         0x3a20,
 237         0x3a22,
 238         0x3a25,
 239         0x3a26,
 240         0,
 241 };
 242
 243 static const struct pci_driver pch_sata __pci_driver = {
 244         .ops     = &sata_ops,
 245         .vendor  = PCI_VID_INTEL,
 246         .devices = pci_device_ids,
 247 };