soc/intel/xeon_sp: Revise IIO domain ACPI name encoding
[coreboot2.git] / payloads / libpayload / include / arm64 / arch / io.h
blob9d67716f89b49cbecd037c32d583bdabe1ac4f65
1 /*
3 * Copyright (C) 2008 Advanced Micro Devices, Inc.
4 * Copyright (C) 2008 coresystems GmbH
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
30 #ifndef _ARCH_IO_H
31 #define _ARCH_IO_H
33 #include <stdint.h>
34 #include <arch/cache.h>
35 #include <arch/lib_helpers.h>
38 * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32
39 * instead for future development.
41 * TODO: make the existing code use read8/16/32 and write8/16/32 then remove
42 * readb/w/l and writeb/w/l.
45 static inline uint8_t readb(volatile const void *_a)
47 dmb();
48 return *(volatile const uint8_t *)_a;
51 static inline uint16_t readw(volatile const void *_a)
53 dmb();
54 return *(volatile const uint16_t *)_a;
57 static inline uint32_t readl(volatile const void *_a)
59 dmb();
60 return *(volatile const uint32_t *)_a;
63 static inline void writeb(uint8_t _v, volatile void *_a)
65 dmb();
66 *(volatile uint8_t *)_a = _v;
67 dmb();
70 static inline void writew(uint16_t _v, volatile void *_a)
72 dmb();
73 *(volatile uint16_t *)_a = _v;
74 dmb();
77 static inline void writel(uint32_t _v, volatile void *_a)
79 dmb();
80 *(volatile uint32_t *)_a = _v;
81 dmb();
84 static inline uint8_t read8(volatile const void *addr)
86 dmb();
87 return *(volatile uint8_t *)addr;
90 static inline uint16_t read16(volatile const void *addr)
92 dmb();
93 return *(volatile uint16_t *)addr;
96 static inline uint32_t read32(volatile const void *addr)
98 dmb();
99 return *(volatile uint32_t *)addr;
102 static inline uint64_t read64(volatile const void *addr)
104 dmb();
105 return *(volatile uint64_t *)addr;
108 static inline void write8(volatile void *addr, uint8_t val)
110 dmb();
111 *(volatile uint8_t *)addr = val;
112 dmb();
115 static inline void write16(volatile void *addr, uint16_t val)
117 dmb();
118 *(volatile uint16_t *)addr = val;
119 dmb();
122 static inline void write32(volatile void *addr, uint32_t val)
124 dmb();
125 *(volatile uint32_t *)addr = val;
126 dmb();
129 static inline void write64(volatile void *addr, uint64_t val)
131 dmb();
132 *(volatile uint64_t *)addr = val;
133 dmb();
136 #endif