src/include/cpu/x86/mtrr.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef CPU_X86_MTRR_H
   4 #define CPU_X86_MTRR_H
   5
   6 #ifndef __ASSEMBLER__
   7 #include <cpu/x86/msr.h>
   8 #include <arch/cpu.h>
   9 #endif
  10
  11 /*  These are the region types  */
  12 #define MTRR_TYPE_UNCACHEABLE           0
  13 #define MTRR_TYPE_WRCOMB                1
  14 #define MTRR_TYPE_WRTHROUGH             4
  15 #define MTRR_TYPE_WRPROT                5
  16 #define MTRR_TYPE_WRBACK                6
  17 #define MTRR_NUM_TYPES                  7
  18
  19 #define MTRR_CAP_MSR                    0x0fe
  20
  21 #define MTRR_CAP_PRMRR                  (1 << 12)
  22 #define MTRR_CAP_SMRR                   (1 << 11)
  23 #define MTRR_CAP_WC                     (1 << 10)
  24 #define MTRR_CAP_FIX                    (1 << 8)
  25 #define MTRR_CAP_VCNT                   0xff
  26
  27 #define MTRR_DEF_TYPE_MSR               0x2ff
  28 #define MTRR_DEF_TYPE_MASK              0xff
  29 #define MTRR_DEF_TYPE_EN                (1 << 11)
  30 #define MTRR_DEF_TYPE_FIX_EN            (1 << 10)
  31
  32 #define IA32_SMRR_PHYS_BASE             0x1f2
  33 #define IA32_SMRR_PHYS_MASK             0x1f3
  34 #define SMRR_PHYS_MASK_LOCK             (1 << 10)
  35
  36 /* Specific to model_6fx and model_1067x.
  37    These are named MSR_SMRR_PHYSBASE in the SDM. */
  38 #define CORE2_SMRR_PHYS_BASE            0xa0
  39 #define CORE2_SMRR_PHYS_MASK            0xa1
  40
  41 #define MTRR_PHYS_BASE(reg)             (0x200 + 2 * (reg))
  42 #define MTRR_PHYS_MASK(reg)             (MTRR_PHYS_BASE(reg) + 1)
  43 #define  MTRR_PHYS_MASK_VALID           (1 << 11)
  44
  45 #define NUM_FIXED_RANGES                88
  46 #define RANGES_PER_FIXED_MTRR           8
  47 #define NUM_FIXED_MTRRS                 (NUM_FIXED_RANGES / RANGES_PER_FIXED_MTRR)
  48 #define MTRR_FIX_64K_00000              0x250
  49 #define MTRR_FIX_16K_80000              0x258
  50 #define MTRR_FIX_16K_A0000              0x259
  51 #define MTRR_FIX_4K_C0000               0x268
  52 #define MTRR_FIX_4K_C8000               0x269
  53 #define MTRR_FIX_4K_D0000               0x26a
  54 #define MTRR_FIX_4K_D8000               0x26b
  55 #define MTRR_FIX_4K_E0000               0x26c
  56 #define MTRR_FIX_4K_E8000               0x26d
  57 #define MTRR_FIX_4K_F0000               0x26e
  58 #define MTRR_FIX_4K_F8000               0x26f
  59
  60 #if !defined(__ASSEMBLER__)
  61
  62 #include <stdint.h>
  63 #include <stddef.h>
  64
  65 /*
  66  * The MTRR code has some side effects that the callers should be aware for.
  67  * 1. The call sequence matters. x86_setup_mtrrs() calls
  68  *    x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
  69  *    of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
  70  *    want to call the components of x86_setup_mtrrs() because of other
  71  *    requirements the ordering should still preserved.
  72  * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
  73  *    of the nature of the global MTRR enable flag. Therefore, all direct
  74  *    or indirect callers of enable_fixed_mtrr() should ensure that the
  75  *    variable MTRR MSRs do not contain bad ranges.
  76  *
  77  * Note that this function sets up MTRRs for addresses above 4GiB.
  78  */
  79 void x86_setup_mtrrs(void);
  80 /*
  81  * x86_setup_mtrrs_with_detect() does the same thing as x86_setup_mtrrs(), but
  82  * it always dynamically detects the number of variable MTRRs available.
  83  */
  84 void x86_setup_mtrrs_with_detect(void);
  85 void x86_setup_mtrrs_with_detect_no_above_4gb(void);
  86 /*
  87  * x86_setup_var_mtrrs() parameters:
  88  * address_bits - number of physical address bits supported by cpu
  89  * above4gb - if set setup MTRRs for addresses above 4GiB else ignore
  90  *            memory ranges above 4GiB
  91  */
  92 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
  93 void enable_fixed_mtrr(void);
  94 /* Unhide Rd/WrDram bits and allow modification for AMD. */
  95 void fixed_mtrrs_expose_amd_rwdram(void);
  96 /* Hide Rd/WrDram bits and allow modification for AMD. */
  97 void fixed_mtrrs_hide_amd_rwdram(void);
  98
  99 void x86_mtrr_check(void);
 100
 101 /* Insert a temporary MTRR range for the duration of coreboot's runtime.
 102  * This function needs to be called after the first MTRR solution is derived. */
 103 void mtrr_use_temp_range(uintptr_t begin, size_t size, int type);
 104
 105 static inline int get_var_mtrr_count(void)
 106 {
 107         return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT;
 108 }
 109
 110 void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
 111         unsigned int type);
 112 int get_free_var_mtrr(void);
 113 void clear_all_var_mtrr(void);
 114
 115 asmlinkage void display_mtrrs(void);
 116
 117 struct var_mtrr_context {
 118         uint32_t max_var_mtrrs;
 119         uint32_t used_var_mtrrs;
 120         struct {
 121                 msr_t base;
 122                 msr_t mask;
 123         } mtrr[];
 124 };
 125
 126 void var_mtrr_context_init(struct var_mtrr_context *ctx);
 127 int var_mtrr_set(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, int type);
 128 void commit_mtrr_setup(const struct var_mtrr_context *ctx);
 129 void postcar_mtrr_setup(void);
 130
 131 /* fms: find most significant bit set, stolen from Linux Kernel Source. */
 132 static inline unsigned int fms(unsigned int x)
 133 {
 134         unsigned int r;
 135
 136         __asm__("bsrl %1,%0\n\t"
 137                 "jnz 1f\n\t"
 138                 "movl $0,%0\n"
 139                 "1:" : "=r" (r) : "mr" (x));
 140         return r;
 141 }
 142
 143 /* fls: find least significant bit set */
 144 static inline unsigned int fls(unsigned int x)
 145 {
 146         unsigned int r;
 147
 148         __asm__("bsfl %1,%0\n\t"
 149                 "jnz 1f\n\t"
 150                 "movl $32,%0\n"
 151                 "1:" : "=r" (r) : "mr" (x));
 152         return r;
 153 }
 154 #endif /* !defined(__ASSEMBLER__) */
 155
 156 /* Align up/down to next power of 2, suitable for assembler
 157    too. Range of result 256kB to 128MB is good enough here. */
 158 #define _POW2_MASK(x)   ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \
 159                                         (x>>6)|(x>>7)|(x>>8)|((1<<18)-1))
 160 #define _ALIGN_UP_POW2(x)       ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
 161 #define _ALIGN_DOWN_POW2(x)     ((x) & ~_POW2_MASK(x))
 162
 163 /* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */
 164 #define _FROM_4G_TOP(x) ((0xffffffff - (x)) + 1)
 165
 166 /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set
 167  * as write-back cacheable to speed up ramstage decompression.
 168  * Note MTRR boundaries, must be power of two.
 169  */
 170 #define CACHE_TMP_RAMTOP (16<<20)
 171
 172 /* For ROM caching, generally, try to use the next power of 2. */
 173 #define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
 174 #define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE)
 175 #if (OPTIMAL_CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || \
 176     (OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE))
 177 # error "Optimal CACHE_ROM_SIZE can't be derived, _POW2_MASK needs refinement."
 178 #endif
 179
 180 /* Make sure it doesn't overlap CAR, though. If the gap between
 181    CAR and 4GiB is too small, make it at most the size of this
 182    gap. As we can't align up (might overlap again), align down
 183    to get a power of 2 again, for a single MTRR. */
 184 #define CAR_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
 185 #if CAR_END > OPTIMAL_CACHE_ROM_BASE
 186 # define CAR_CACHE_ROM_SIZE _ALIGN_DOWN_POW2(_FROM_4G_TOP(CAR_END))
 187 #else
 188 # define CAR_CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE
 189 #endif
 190 #if ((CAR_CACHE_ROM_SIZE & (CAR_CACHE_ROM_SIZE - 1)) != 0)
 191 # error "CAR CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement."
 192 #endif
 193
 194 /* Last but not least, most (if not all) chipsets have MMIO
 195    between 0xfe000000 and 0xff000000, so limit to 16MiB. */
 196 #if CAR_CACHE_ROM_SIZE >= 16 << 20
 197 # define CACHE_ROM_SIZE (16 << 20)
 198 #else
 199 # define CACHE_ROM_SIZE CAR_CACHE_ROM_SIZE
 200 #endif
 201
 202 #define CACHE_ROM_BASE _FROM_4G_TOP(CACHE_ROM_SIZE)
 203
 204 #endif /* CPU_X86_MTRR_H */