src/northbridge/intel/sandybridge/northbridge.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cpu/cpu.h>
   4 #include <console/console.h>
   5 #include <acpi/acpi.h>
   6 #include <acpi/acpigen.h>
   7 #include <commonlib/helpers.h>
   8 #include <device/pci_ops.h>
   9 #include <delay.h>
  10 #include <cpu/intel/model_206ax/model_206ax.h>
  11 #include <cpu/x86/msr.h>
  12 #include <device/device.h>
  13 #include <device/pci.h>
  14 #include <device/pci_ids.h>
  15 #include <types.h>
  16 #include "chip.h"
  17 #include "sandybridge.h"
  18 #include <cpu/intel/smm_reloc.h>
  19 #include <security/intel/txt/txt_platform.h>
  20
  21 /* IGD UMA memory */
  22 static uint64_t uma_memory_base = 0;
  23 static uint64_t uma_memory_size = 0;
  24
  25 bool is_sandybridge(void)
  26 {
  27         const uint16_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID);
  28
  29         return (bridge_id & BASE_REV_MASK) == BASE_REV_SNB;
  30 }
  31
  32 /* Reserve everything between A segment and 1MB:
  33  *
  34  * 0xa0000 - 0xbffff: legacy VGA
  35  * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
  36  * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
  37  */
  38
  39 static const char *northbridge_acpi_name(const struct device *dev)
  40 {
  41         if (dev->path.type == DEVICE_PATH_DOMAIN)
  42                 return "PCI0";
  43
  44         if (dev->path.type != DEVICE_PATH_PCI)
  45                 return NULL;
  46
  47         switch (dev->path.pci.devfn) {
  48         case PCI_DEVFN(0, 0):
  49                 return "MCHC";
  50         }
  51
  52         return NULL;
  53 }
  54
  55 struct device_operations sandybridge_pci_domain_ops = {
  56         .read_resources    = pci_domain_read_resources,
  57         .set_resources     = pci_domain_set_resources,
  58         .scan_bus          = pci_host_bridge_scan_bus,
  59         .write_acpi_tables = northbridge_write_acpi_tables,
  60         .acpi_name         = northbridge_acpi_name,
  61 };
  62
  63 static void add_fixed_resources(struct device *dev, int index)
  64 {
  65         mmio_resource_kb(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
  66
  67         mmio_from_to(dev, index++, 0xa0000, 0xc0000);
  68         reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
  69
  70         if (is_sandybridge()) {
  71                 /* Required for SandyBridge sighting 3715511 */
  72                 bad_ram_resource_kb(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
  73                 bad_ram_resource_kb(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
  74         }
  75
  76         /* Reserve IOMMU BARs */
  77         const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
  78         if (!(capid0_a & (1 << 23))) {
  79                 mmio_resource_kb(dev, index++, GFXVT_BASE >> 10, 4);
  80                 mmio_resource_kb(dev, index++, VTVC0_BASE >> 10, 4);
  81         }
  82 }
  83
  84 static uint64_t get_touud(const struct device *dev)
  85 {
  86         uint64_t touud = pci_read_config32(dev, TOUUD + 4);
  87         touud <<= 32;
  88         touud |= pci_read_config32(dev, TOUUD) & 0xfff00000;
  89         return touud;
  90 }
  91
  92 static void mc_read_resources(struct device *dev)
  93 {
  94         uint64_t tom, me_base, touud;
  95         uint32_t tseg_base, uma_size, tolud;
  96         uint32_t dpr_base_k, dpr_size_k;
  97         uint16_t ggc;
  98         unsigned long long tomk;
  99         unsigned long index = 3;
 100         const union dpr_register dpr = txt_get_chipset_dpr();
 101
 102         pci_dev_read_resources(dev);
 103
 104         mmconf_resource(dev, PCIEXBAR);
 105
 106         /* Total Memory 2GB example:
 107          *
 108          *  00000000  0000MB-1992MB  1992MB  RAM     (writeback)
 109          *  7c800000  1992MB-2000MB     8MB  TSEG    (SMRR)
 110          *  7d000000  2000MB-2002MB     2MB  GFX GTT (uncached)
 111          *  7d200000  2002MB-2034MB    32MB  GFX UMA (uncached)
 112          *  7f200000   2034MB TOLUD
 113          *  7f800000   2040MB MEBASE
 114          *  7f800000  2040MB-2048MB     8MB  ME UMA  (uncached)
 115          *  80000000   2048MB TOM
 116          * 100000000  4096MB-4102MB     6MB  RAM     (writeback)
 117          *
 118          * Total Memory 4GB example:
 119          *
 120          *  00000000  0000MB-2768MB  2768MB  RAM     (writeback)
 121          *  ad000000  2768MB-2776MB     8MB  TSEG    (SMRR)
 122          *  ad800000  2776MB-2778MB     2MB  GFX GTT (uncached)
 123          *  ada00000  2778MB-2810MB    32MB  GFX UMA (uncached)
 124          *  afa00000   2810MB TOLUD
 125          *  ff800000   4088MB MEBASE
 126          *  ff800000  4088MB-4096MB     8MB  ME UMA  (uncached)
 127          * 100000000   4096MB TOM
 128          * 100000000  4096MB-5374MB  1278MB  RAM     (writeback)
 129          * 14fe00000   5368MB TOUUD
 130          */
 131
 132         /* Top of Upper Usable DRAM, including remap */
 133         touud  = get_touud(dev);
 134
 135         /* Top of Lower Usable DRAM */
 136         tolud = pci_read_config32(dev, TOLUD);
 137
 138         /* Top of Memory - does not account for any UMA */
 139         tom  = pci_read_config32(dev, TOM + 4);
 140         tom <<= 32;
 141         tom |= pci_read_config32(dev, TOM);
 142
 143         printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
 144                touud, tolud, tom);
 145
 146         /* ME UMA needs excluding if total memory < 4GB */
 147         me_base  = pci_read_config32(dev, MESEG_BASE + 4);
 148         me_base <<= 32;
 149         me_base |= pci_read_config32(dev, MESEG_BASE);
 150
 151         printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base);
 152
 153         uma_memory_base = tolud;
 154         tomk = tolud >> 10;
 155         if (me_base == tolud) {
 156                 /* ME is from MEBASE-TOM */
 157                 uma_size = (tom - me_base) >> 10;
 158                 /* Increment TOLUD to account for ME as RAM */
 159                 tolud += uma_size << 10;
 160                 /* UMA starts at old TOLUD */
 161                 uma_memory_base = tomk * 1024ULL;
 162                 uma_memory_size = uma_size * 1024ULL;
 163                 printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n",
 164                        me_base, uma_size >> 10);
 165         }
 166
 167         /* Graphics memory comes next */
 168         ggc = pci_read_config16(dev, GGC);
 169         if (!(ggc & 2)) {
 170                 printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 171
 172                 /* Graphics memory */
 173                 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
 174                 printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10);
 175                 tomk -= uma_size;
 176                 uma_memory_base = tomk * 1024ULL;
 177                 uma_memory_size += uma_size * 1024ULL;
 178
 179                 /* GTT Graphics Stolen Memory Size (GGMS) */
 180                 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
 181                 tomk -= uma_size;
 182                 uma_memory_base = tomk * 1024ULL;
 183                 uma_memory_size += uma_size * 1024ULL;
 184                 printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10);
 185         }
 186
 187         /* Calculate TSEG size from its base which must be below GTT */
 188         tseg_base = pci_read_config32(dev, TSEGMB);
 189         uma_size = (uma_memory_base - tseg_base) >> 10;
 190         tomk -= uma_size;
 191         uma_memory_base = tomk * 1024ULL;
 192         uma_memory_size += uma_size * 1024ULL;
 193         printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
 194
 195         /* Calculate DMA Protected Region if enabled */
 196         if (dpr.epm && dpr.size) {
 197                 dpr_size_k = dpr.size * MiB / KiB;
 198                 tomk -= dpr_size_k;
 199                 dpr_base_k = (tseg_base - dpr.size * MiB) / KiB;
 200                 reserved_ram_resource_kb(dev, index++, dpr_base_k, dpr_size_k);
 201                 printk(BIOS_DEBUG, "DPR base 0x%08x size %uM\n", dpr_base_k * KiB, dpr.size);
 202         }
 203
 204         printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
 205
 206         /* Report the memory regions */
 207         ram_from_to(dev, index++, 0, 0xa0000);
 208         ram_from_to(dev, index++, 1 * MiB, tomk * KiB);
 209
 210         /*
 211          * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM.
 212          * TOUUD will account for both memory chunks.
 213          */
 214         upper_ram_end(dev, index++, touud);
 215
 216         add_fixed_resources(dev, index++);
 217 }
 218
 219 static void northbridge_dmi_init(struct device *dev)
 220 {
 221         const bool is_sandy = is_sandybridge();
 222
 223         const u8 stepping = cpu_stepping();
 224
 225         /* Steps prior to DMI ASPM */
 226         if (is_sandy) {
 227                 dmibar_clrsetbits32(0x250, 7 << 20, 2 << 20);
 228         }
 229
 230         dmibar_setbits32(DMILLTC, 1 << 29);
 231
 232         if (is_sandy && stepping == SNB_STEP_C0) {
 233                 dmibar_clrsetbits32(0xbc8, 0xfff << 7, 0x7d3 << 7);
 234         }
 235
 236         if (!is_sandy || stepping >= SNB_STEP_D1) {
 237                 dmibar_clrsetbits32(0x1f8, 1 << 26, 1 << 16);
 238
 239                 dmibar_setbits32(0x1fc, 1 << 12 | 1 << 23);
 240
 241         } else if (stepping >= SNB_STEP_D0) {
 242                 dmibar_setbits32(0x1f8, 1 << 16);
 243         }
 244
 245         /* Clear error status bits */
 246         dmibar_write32(DMIUESTS, 0xffffffff);
 247         dmibar_write32(DMICESTS, 0xffffffff);
 248
 249         if (!is_sandy)
 250                 dmibar_write32(0xc34, 0xffffffff);
 251
 252         /* Enable ASPM on SNB link, should happen before PCH link */
 253         if (is_sandy) {
 254                 dmibar_setbits32(0xd04, 1 << 4);
 255         }
 256
 257         dmibar_setbits32(DMILCTL, 1 << 1 | 1 << 0);
 258 }
 259
 260 /* Disable unused PEG devices based on devicetree */
 261 static void disable_peg(void)
 262 {
 263         struct device *dev;
 264         u32 reg;
 265
 266         dev = pcidev_on_root(0, 0);
 267         reg = pci_read_config32(dev, DEVEN);
 268
 269         dev = pcidev_on_root(1, 2);
 270         if (!dev || !dev->enabled) {
 271                 printk(BIOS_DEBUG, "Disabling PEG12.\n");
 272                 reg &= ~DEVEN_PEG12;
 273         }
 274         dev = pcidev_on_root(1, 1);
 275         if (!dev || !dev->enabled) {
 276                 printk(BIOS_DEBUG, "Disabling PEG11.\n");
 277                 reg &= ~DEVEN_PEG11;
 278         }
 279         dev = pcidev_on_root(1, 0);
 280         if (!dev || !dev->enabled) {
 281                 printk(BIOS_DEBUG, "Disabling PEG10.\n");
 282                 reg &= ~DEVEN_PEG10;
 283         }
 284         dev = pcidev_on_root(2, 0);
 285         if (!dev || !dev->enabled) {
 286                 printk(BIOS_DEBUG, "Disabling IGD.\n");
 287                 reg &= ~DEVEN_IGD;
 288         }
 289         dev = pcidev_on_root(4, 0);
 290         if (!dev || !dev->enabled) {
 291                 printk(BIOS_DEBUG, "Disabling Device 4.\n");
 292                 reg &= ~DEVEN_D4EN;
 293         }
 294         dev = pcidev_on_root(6, 0);
 295         if (!dev || !dev->enabled) {
 296                 printk(BIOS_DEBUG, "Disabling PEG60.\n");
 297                 reg &= ~DEVEN_PEG60;
 298         }
 299         dev = pcidev_on_root(7, 0);
 300         if (!dev || !dev->enabled) {
 301                 printk(BIOS_DEBUG, "Disabling Device 7.\n");
 302                 reg &= ~DEVEN_D7EN;
 303         }
 304
 305         dev = pcidev_on_root(0, 0);
 306         pci_write_config32(dev, DEVEN, reg);
 307
 308         if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) {
 309                 /*
 310                  * Set the PEG clock gating bit. Disables the IO clock on all PEG devices.
 311                  *
 312                  * FIXME: Never clock gate on Ivy Bridge stepping A0!
 313                  */
 314                 mchbar_setbits32(PEGCTL, 1);
 315                 printk(BIOS_DEBUG, "Disabling PEG IO clock.\n");
 316         } else {
 317                 mchbar_clrbits32(PEGCTL, 1);
 318         }
 319 }
 320
 321 static void northbridge_init(struct device *dev)
 322 {
 323         u32 bridge_type;
 324
 325         northbridge_dmi_init(dev);
 326
 327         bridge_type = mchbar_read32(SAPMTIMERS);
 328         bridge_type &= ~0xff;
 329
 330         if (is_sandybridge()) {
 331                 /* 20h for Sandybridge */
 332                 bridge_type |= 0x20;
 333         } else {
 334                 /* Enable Power Aware Interrupt Routing */
 335                 mchbar_clrsetbits8(INTRDIRCTL, 0xf, 0x4); /* Clear 3:0, set Fixed Priority */
 336
 337                 /* 30h for IvyBridge */
 338                 bridge_type |= 0x30;
 339         }
 340         mchbar_write32(SAPMTIMERS, bridge_type);
 341
 342         /* Turn off unused devices. Has to be done before setting BIOS_RESET_CPL. */
 343         disable_peg();
 344
 345         /*
 346          * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
 347          * that BIOS has initialized memory and power management
 348          */
 349         mchbar_setbits8(BIOS_RESET_CPL, 1 << 0);
 350         printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
 351
 352         /* Configure turbo power limits 1ms after reset complete bit */
 353         mdelay(1);
 354         set_power_limits(28);
 355
 356         /*
 357          * CPUs with configurable TDP also need power limits set in MCHBAR.
 358          * Use the same values from MSR_PKG_POWER_LIMIT.
 359          */
 360         if (cpu_config_tdp_levels()) {
 361                 msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT);
 362                 mchbar_write32(MCH_PKG_POWER_LIMIT_LO, msr.lo);
 363                 mchbar_write32(MCH_PKG_POWER_LIMIT_HI, msr.hi);
 364         }
 365
 366         /* Set here before graphics PM init */
 367         mchbar_write32(PAVP_MSG, 0x00100001);
 368 }
 369
 370 void northbridge_write_smram(u8 smram)
 371 {
 372         pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);
 373 }
 374
 375 static void set_above_4g_pci(const struct device *dev)
 376 {
 377         const uint64_t touud = get_touud(dev);
 378         const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud;
 379
 380         acpigen_write_scope("\\");
 381         acpigen_write_name_qword("A4GB", touud);
 382         acpigen_write_name_qword("A4GS", len);
 383         acpigen_pop_len();
 384
 385         printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len);
 386 }
 387
 388 static void mc_gen_ssdt(const struct device *dev)
 389 {
 390         set_above_4g_pci(dev);
 391 }
 392
 393 struct device_operations sandybridge_host_bridge_ops = {
 394         .read_resources         = mc_read_resources,
 395         .set_resources          = pci_dev_set_resources,
 396         .enable_resources       = pci_dev_enable_resources,
 397         .init                   = northbridge_init,
 398         .ops_pci                = &pci_dev_ops_pci,
 399         .acpi_fill_ssdt         = mc_gen_ssdt,
 400 };
 401
 402 struct device_operations sandybridge_cpu_bus_ops = {
 403         .read_resources   = noop_read_resources,
 404         .set_resources    = noop_set_resources,
 405         .init             = mp_cpu_bus_init,
 406         .acpi_fill_ssdt   = generate_cpu_entries,
 407 };
 408
 409 struct chip_operations northbridge_intel_sandybridge_ops = {
 410         CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge")
 411 };