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soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / .gitreview
blob5d4fcd823f4e6519e6596901c2f0e53d86e5f21d
1 [gerrit]
2 host=review.coreboot.org
3 port=29418
4 project=coreboot
5 defaultbranch=main
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