soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / configs / config.asrock_b85m_pro4.tpm2_txt_placeholder_acms
blobda33450e01c72186492462817f524b0a7d258914
1 # Known-working configuration to boot with TXT enabled. Since BIOS
2 # and SINIT ACM blobs are missing, use something else as placeholder.
3 # Used ACMs were extracted from a Supermicro X10SLH firmware update.
5 # CONFIG_TPM_PPI=y tests building PPI implementation.
6 CONFIG_VENDOR_ASROCK=y
7 CONFIG_BOARD_ASROCK_B85M_PRO4=y
8 CONFIG_TPM_PPI=y
9 CONFIG_TPM2=y
10 CONFIG_INTEL_TXT=y
11 CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin"
12 CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin"
13 CONFIG_INTEL_TXT_LOGGING=y