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HEAD
soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git]
/
configs
/
config.google_vilboz.x86_64
blob
ddb2edacd95304f1e4cac86aaaf8f0040daa4653
1
CONFIG_VENDOR_GOOGLE=y
2
CONFIG_BOARD_GOOGLE_VILBOZ=y
3
CONFIG_USE_X86_64_SUPPORT=y
