soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / configs / config.google_volteer.build_test_purposes
blob6843aeb2893f00cfb16d4fc4ad67222ce0eef1e7
1 # Not meant for actual use, but rather to build-test individual options.
2 # If keeping this combination of options buildable becomes too hard in
3 # the future, then this config can be split into several smaller chunks.
4 # Exercises, among other things:
5 # + Debug options
6 # + Crashlog
7 # + Flashconsole
8 CONFIG_VENDOR_GOOGLE=y
9 CONFIG_CONSOLE_POST=y
10 CONFIG_BOARD_GOOGLE_VOLTEER=y
11 CONFIG_USE_LEGACY_8254_TIMER=y
12 CONFIG_INTEL_TME=y
13 CONFIG_SOC_INTEL_CRASHLOG=y
14 CONFIG_NO_GFX_INIT=y
15 CONFIG_DISPLAY_HOBS=y
16 CONFIG_DISPLAY_UPD_DATA=y
17 CONFIG_CONSOLE_SPI_FLASH=y
18 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
19 CONFIG_DISPLAY_MTRRS=y
20 CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
21 CONFIG_DISPLAY_FSP_HEADER=y
22 CONFIG_VERIFY_HOBS=y
23 CONFIG_FATAL_ASSERTS=y
24 CONFIG_DEBUG_GPIO=y
25 CONFIG_DEBUG_CBFS=y
26 CONFIG_DEBUG_SMBUS=y
27 CONFIG_DEBUG_SMI=y
28 CONFIG_DEBUG_PERIODIC_SMI=y
29 CONFIG_DEBUG_MALLOC=y
30 CONFIG_DEBUG_CONSOLE_INIT=y
31 CONFIG_DEBUG_SPI_FLASH=y
32 CONFIG_DEBUG_BOOT_STATE=y
33 CONFIG_CBFS_VERIFICATION=y