soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / configs / config.msi_ms7e06_ddr4
bloba6080b93a9ac9c0792d42e04d16546952767dc46
1 CONFIG_VENDOR_MSI=y
2 CONFIG_VBOOT=y
3 CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR4=y
4 CONFIG_TPM_MEASURED_BOOT=y
5 CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
6 CONFIG_TPM2=y
7 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
8 CONFIG_PAYLOAD_EDK2=y
9 CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
10 CONFIG_EDK2_CBMEM_LOGGING=y
11 CONFIG_EDK2_FOLLOW_BGRT_SPEC=y