soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / configs / config.pcengines_apu3
blobbf377158dfea548b714a588024f0ab0b948405f6
1 # CONFIG_COLLECT_TIMESTAMPS is not set
2 CONFIG_VENDOR_PCENGINES=y
3 CONFIG_BOARD_PCENGINES_APU3=y
4 CONFIG_APU2_PINMUX_UART_C=y
5 CONFIG_APU2_PINMUX_UART_D=y
6 CONFIG_NO_GFX_INIT=y
7 CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
8 CONFIG_PXE=y
9 CONFIG_BUILD_IPXE=y
10 CONFIG_PXE_ROM_ID="8086,1539"
11 # CONFIG_IPXE_SERIAL_CONSOLE is not set
12 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y