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soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / configs / config.sifive_hifive-unleashed.opensbi
blob3772792e3bbac0a5c54076c884b70372dfca961a
1 CONFIG_VENDOR_SIFIVE=y
2 CONFIG_BOARD_SIFIVE_HIFIVE_UNLEASHED=y
3 CONFIG_RISCV_OPENSBI=y
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