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soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git]
/
util
/
autoport
/
description.md
blob
361a9f2d155aa02f5949b2bc229aa53e0ce79259
1
Automated porting coreboot to Sandy Bridge/Ivy Bridge/Haswell platforms `Go`
