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HEAD
soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git]
/
util
/
autoport
/
ec_none.go
blob
a1a0df94f07e763cba97be660b598b5406edf42d
1
package
main
2
3
func
NoEC
(
ctx Context
) {
4
ap
:=
Create
(
ctx
,
"acpi/platform.asl"
)
5
defer
ap
.
Close
()
6
7
Add_SPDX
(
ap
,
ASL
,
GPL2_only
)
8
ap
.
WriteString
(
9
`Method(_WAK, 1)
10
{
11
Return(Package() {0, 0})
12
}
13
14
Method(_PTS, 1)
15
{
16
}
17
`
)
18
19
si
:=
Create
(
ctx
,
"acpi/superio.asl"
)
20
defer
si
.
Close
()
21
22
ec
:=
Create
(
ctx
,
"acpi/ec.asl"
)
23
defer
ec
.
Close
()
24
}