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soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git]
/
util
/
inteltool
/
description.md
blob
bf1126666dc1188437a77be00e9d84b0049bca18
1
Provides information about the Intel CPU/chipset hardware configuration
2
(register contents, MSRs, etc). `C`
