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soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / util / inteltool / gpio.c
blobcd6ce911851c24dd9397f2a66354dab6596cadb7
1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /* SPDX-License-Identifier: GPL-2.0-only */
3
4 #include <stdio.h>
5 #include "inteltool.h"
6
7 typedef struct { uint16_t addr; uint32_t def; } gpio_default_t;
8
9 static const io_register_t ich0_gpio_registers[] = {
10 { 0x00, 4, "GPIO_USE_SEL" },
11 { 0x04, 4, "GP_IO_SEL" },
12 { 0x08, 4, "RESERVED" },
13 { 0x0c, 4, "GP_LVL" },
14 { 0x10, 4, "RESERVED" },
15 { 0x14, 4, "GPO_TTL" },
16 { 0x18, 4, "GPO_BLINK" },
17 { 0x1c, 4, "RESERVED" },
18 { 0x20, 4, "RESERVED" },
19 { 0x24, 4, "RESERVED" },
20 { 0x28, 4, "RESERVED" },
21 { 0x2c, 4, "GPI_INV" },
22 { 0x30, 4, "RESERVED" },
23 { 0x34, 4, "RESERVED" },
24 { 0x38, 4, "RESERVED" },
25 { 0x3C, 4, "RESERVED" }
26 };
27
28 static const io_register_t ich2_gpio_registers[] = {
29 { 0x00, 4, "GPIO_USE_SEL" },
30 { 0x04, 4, "GP_IO_SEL" },
31 { 0x08, 4, "RESERVED" },
32 { 0x0c, 4, "GP_LVL" },
33 { 0x10, 4, "RESERVED" },
34 { 0x14, 4, "GPO_TTL" },
35 { 0x18, 4, "GPO_BLINK" },
36 { 0x1c, 4, "RESERVED" },
37 { 0x20, 4, "RESERVED" },
38 { 0x24, 4, "RESERVED" },
39 { 0x28, 4, "RESERVED" },
40 { 0x2c, 4, "GPI_INV" },
41 { 0x30, 4, "RESERVED" },
42 { 0x34, 4, "RESERVED" },
43 { 0x38, 4, "RESERVED" },
44 { 0x3C, 4, "RESERVED" }
45 };
46
47 static const io_register_t ich4_gpio_registers[] = {
48 { 0x00, 4, "GPIO_USE_SEL" },
49 { 0x04, 4, "GP_IO_SEL" },
50 { 0x08, 4, "RESERVED" },
51 { 0x0c, 4, "GP_LVL" },
52 { 0x10, 4, "RESERVED" },
53 { 0x14, 4, "GPO_TTL" },
54 { 0x18, 4, "GPO_BLINK" },
55 { 0x1c, 4, "RESERVED" },
56 { 0x20, 4, "RESERVED" },
57 { 0x24, 4, "RESERVED" },
58 { 0x28, 4, "RESERVED" },
59 { 0x2c, 4, "GPI_INV" },
60 { 0x30, 4, "GPIO_USE_SEL2" },
61 { 0x34, 4, "GP_IO_SEL2" },
62 { 0x38, 4, "GP_LVL2" },
63 { 0x3C, 4, "RESERVED" }
64 };
65
66 static const io_register_t ich5_gpio_registers[] = {
67 { 0x00, 4, "GPIO_USE_SEL" },
68 { 0x04, 4, "GP_IO_SEL" },
69 { 0x08, 4, "RESERVED" },
70 { 0x0c, 4, "GP_LVL" },
71 { 0x10, 4, "RESERVED" },
72 { 0x14, 4, "GPO_TTL"},
73 { 0x18, 4, "GPO_BLINK"},
74 { 0x1c, 4, "RESERVED" },
75 { 0x20, 4, "RESERVED" },
76 { 0x2c, 4, "GPI_INV" },
77 { 0x30, 4, "GPIO_USE_SEL2" },
78 { 0x34, 4, "GP_IO_SEL2" },
79 { 0x38, 4, "GP_LVL2" },
80 };
81
82 static const io_register_t ich6_gpio_registers[] = {
83 { 0x00, 4, "GPIO_USE_SEL" },
84 { 0x08, 4, "RESERVED" },
85 { 0x0c, 4, "GP_LVL" },
86 { 0x10, 4, "RESERVED" },
87 { 0x14, 4, "RESERVED" },
88 { 0x18, 4, "GPO_BLINK" },
89 { 0x1c, 4, "RESERVED" },
90 { 0x20, 4, "RESERVED" },
91 { 0x24, 4, "RESERVED" },
92 { 0x28, 4, "RESERVED" },
93 { 0x2c, 4, "GPI_INV" },
94 { 0x30, 4, "GPIO_USE_SEL2" },
95 { 0x34, 4, "GP_IO_SEL2" },
96 { 0x38, 4, "GP_LVL2" },
97 { 0x04, 4, "GP_IO_SEL" },
98 };
99
100 static const io_register_t ich7_gpio_registers[] = {
101 { 0x00, 4, "GPIO_USE_SEL" },
102 { 0x04, 4, "GP_IO_SEL" },
103 { 0x08, 4, "RESERVED" },
104 { 0x0c, 4, "GP_LVL" },
105 { 0x10, 4, "RESERVED" },
106 { 0x14, 4, "RESERVED" },
107 { 0x18, 4, "GPO_BLINK" },
108 { 0x1c, 4, "RESERVED" },
109 { 0x20, 4, "RESERVED" },
110 { 0x24, 4, "RESERVED" },
111 { 0x28, 4, "RESERVED" },
112 { 0x2c, 4, "GPI_INV" },
113 { 0x30, 4, "GPIO_USE_SEL2" },
114 { 0x34, 4, "GP_IO_SEL2" },
115 { 0x38, 4, "GP_LVL2" },
116 { 0x3C, 4, "RESERVED" }
117 };
118
119 static const io_register_t ich8_gpio_registers[] = {
120 { 0x00, 4, "GPIO_USE_SEL" },
121 { 0x04, 4, "GP_IO_SEL" },
122 { 0x08, 4, "RESERVED" },
123 { 0x0c, 4, "GP_LVL" },
124 { 0x10, 4, "GPIO_USE_SEL Override (LOW)" },
125 { 0x14, 4, "RESERVED" },
126 { 0x18, 4, "GPO_BLINK" },
127 { 0x1c, 4, "GP_SER_BLINK" },
128 { 0x20, 4, "GP_SB_CMDSTS" },
129 { 0x24, 4, "GP_SB_DATA" },
130 { 0x28, 4, "RESERVED" },
131 { 0x2c, 4, "GPI_INV" },
132 { 0x30, 4, "GPIO_USE_SEL2" },
133 { 0x34, 4, "GP_IO_SEL2" },
134 { 0x38, 4, "GP_LVL2" },
135 { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
136 };
137
138 static const io_register_t ich9_gpio_registers[] = {
139 { 0x00, 4, "GPIO_USE_SEL" },
140 { 0x04, 4, "GP_IO_SEL" },
141 { 0x08, 4, "RESERVED" },
142 { 0x0c, 4, "GP_LVL" },
143 { 0x10, 4, "RESERVED" },
144 { 0x14, 4, "RESERVED" },
145 { 0x18, 4, "GPO_BLINK" },
146 { 0x1c, 4, "GP_SER_BLINK" },
147 { 0x20, 4, "GP_SB_CMDSTS" },
148 { 0x24, 4, "GP_SB_DATA" },
149 { 0x28, 4, "RESERVED" },
150 { 0x2c, 4, "GPI_INV" },
151 { 0x30, 4, "GPIO_USE_SEL2" },
152 { 0x34, 4, "GP_IO_SEL2" },
153 { 0x38, 4, "GP_LVL2" },
154 { 0x3C, 4, "RESERVED" }
155 };
156
157 static const io_register_t ich10_gpio_registers[] = {
158 { 0x00, 4, "GPIO_USE_SEL" },
159 { 0x04, 4, "GP_IO_SEL" },
160 { 0x08, 4, "RESERVED" },
161 { 0x0c, 4, "GP_LVL" },
162 { 0x10, 4, "RESERVED" },
163 { 0x14, 4, "RESERVED" },
164 { 0x18, 4, "GPO_BLINK" },
165 { 0x1c, 4, "GP_SER_BLINK" },
166 { 0x20, 4, "GP_SB_CMDSTS" },
167 { 0x24, 4, "GP_SB_DATA" },
168 { 0x28, 4, "RESERVED" },
169 { 0x2c, 4, "GPI_INV" },
170 { 0x30, 4, "GPIO_USE_SEL2" },
171 { 0x34, 4, "GP_IO_SEL2" },
172 { 0x38, 4, "GP_LVL2" },
173 { 0x3C, 4, "RESERVED" },
174 { 0x40, 4, "GPIO_USE_SEL3" },
175 { 0x44, 4, "GP_IO_SEL3" },
176 { 0x48, 4, "GP_LVL3" },
177 { 0x4c, 4, "RESERVED" },
178 { 0x50, 4, "RESERVED" },
179 { 0x54, 4, "RESERVED" },
180 { 0x58, 4, "RESERVED" },
181 { 0x5c, 4, "RESERVED" },
182 { 0x60, 4, "GP_RST_SEL" },
183 { 0x64, 4, "RESERVED" },
184 { 0x68, 4, "RESERVED" },
185 { 0x6c, 4, "RESERVED" },
186 { 0x70, 4, "RESERVED" },
187 { 0x74, 4, "RESERVED" },
188 { 0x78, 4, "RESERVED" },
189 { 0x7c, 4, "RESERVED" },
190 };
191
192 static const io_register_t i631x_gpio_registers[] = {
193 { 0x00, 4, "GPIO_USE_SEL" },
194 { 0x04, 4, "GP_IO_SEL" },
195 { 0x08, 4, "RESERVED" },
196 { 0x0c, 4, "GP_LVL" },
197 { 0x10, 4, "RESERVED" },
198 { 0x14, 4, "RESERVED" },
199 { 0x18, 4, "GPO_BLINK" },
200 { 0x1c, 4, "RESERVED" },
201 { 0x20, 4, "RESERVED" },
202 { 0x24, 4, "RESERVED" },
203 { 0x28, 4, "RESERVED" },
204 { 0x2c, 4, "GPI_INV" },
205 { 0x30, 4, "GPIO_USE_SEL2" },
206 { 0x34, 4, "GP_IO_SEL2" },
207 { 0x38, 4, "GP_LVL2" },
208 };
209
210 static const io_register_t pch_gpio_registers[] = {
211 { 0x00, 4, "GPIO_USE_SEL" },
212 { 0x04, 4, "GP_IO_SEL" },
213 { 0x08, 4, "RESERVED" },
214 { 0x0c, 4, "GP_LVL" },
215 { 0x10, 4, "RESERVED" },
216 { 0x14, 4, "RESERVED" },
217 { 0x18, 4, "GPO_BLINK" },
218 { 0x1c, 4, "GP_SER_BLINK" },
219 { 0x20, 4, "GP_SB_CMDSTS" },
220 { 0x24, 4, "GP_SB_DATA" },
221 { 0x28, 2, "GPI_NMI_EN" },
222 { 0x2a, 2, "GPI_NMI_STS" },
223 { 0x2c, 4, "GPI_INV" },
224 { 0x30, 4, "GPIO_USE_SEL2" },
225 { 0x34, 4, "GP_IO_SEL2" },
226 { 0x38, 4, "GP_LVL2" },
227 { 0x3c, 4, "RESERVED" },
228 { 0x40, 4, "GPIO_USE_SEL3" },
229 { 0x44, 4, "GP_IO_SEL3" },
230 { 0x48, 4, "GP_LVL3" },
231 { 0x4c, 4, "RESERVED" },
232 { 0x50, 4, "RESERVED" },
233 { 0x54, 4, "RESERVED" },
234 { 0x58, 4, "RESERVED" },
235 { 0x5c, 4, "RESERVED" },
236 { 0x60, 4, "GP_RST_SEL1" },
237 { 0x64, 4, "GP_RST_SEL2" },
238 { 0x68, 4, "GP_RST_SEL3" },
239 { 0x6c, 4, "RESERVED" },
240 { 0x70, 4, "RESERVED" },
241 { 0x74, 4, "RESERVED" },
242 { 0x78, 4, "RESERVED" },
243 { 0x7c, 4, "RESERVED" },
244 };
245 /* Default values for Ibex Peak desktop chipsets */
246 static const gpio_default_t ip_pch_desktop_defaults[] = {
247 { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */
248 { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */
249 { 0x0c, 0x02fe0100 }, /* GP_LVL */
250 { 0x18, 0x00040000 }, /* GPO_BLINK */
251 { 0x1c, 0x00000000 }, /* GP_SER_BLINK */
252 { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */
253 { 0x2c, 0x00000000 }, /* GP_INV */
254 { 0x30, 0x020300ff }, /* GPIO_USE_SEL2 */
255 { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */
256 { 0x38, 0xa4aa0003 }, /* GP_LVL2 */
257 { 0x40, 0x00000100 }, /* GPIO_USE_SEL3 */
258 { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */
259 { 0x48, 0x00000000 }, /* GP_LVL3 */
260 { 0x60, 0x01000000 }, /* GP_RST_SEL1 */
261 { 0x64, 0x00000000 }, /* GP_RST_SEL2 */
262 { 0x68, 0x00000000 }, /* GP_RST_SEL3 */
263 };
264 /* Default values for Ibex Peak mobile chipsets */
265 static const gpio_default_t ip_pch_mobile_defaults[] = {
266 { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */
267 { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */
268 { 0x0c, 0x02fe0100 }, /* GP_LVL */
269 { 0x18, 0x00040000 }, /* GPO_BLINK */
270 { 0x1c, 0x00000000 }, /* GP_SER_BLINK */
271 { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */
272 { 0x2c, 0x00000000 }, /* GP_INV */
273 { 0x30, 0x020300fe }, /* GPIO_USE_SEL2 */
274 { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */
275 { 0x38, 0xa4aa0003 }, /* GP_LVL2 */
276 { 0x40, 0x00000000 }, /* GPIO_USE_SEL3 */
277 { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */
278 { 0x48, 0x00000000 }, /* GP_LVL3 */
279 { 0x60, 0x01000000 }, /* GP_RST_SEL1 */
280 { 0x64, 0x00000000 }, /* GP_RST_SEL2 */
281 { 0x68, 0x00000000 }, /* GP_RST_SEL3 */
282 };
283
284 static const io_register_t lynxpoint_lp_gpio_registers[] = {
285 { 0x00, 4, "GPIO_OWN1" }, // GPIO Ownership
286 { 0x04, 4, "GPIO_OWN2" }, // GPIO Ownership
287 { 0x08, 4, "GPIO_OWN3" }, // GPIO Ownership
288 { 0x0c, 4, "RESERVED" }, // Reserved
289 { 0x10, 2, "GPIPRIOQ2IOXAPIC" }, // GPI PIRQ[X:I] to IOxAPIC[39:24] Enable
290 { 0x12, 2, "RESERVED" }, // Reserved
291 { 0x14, 4, "RESERVED" }, // Reserved
292 { 0x18, 4, "GPO_BLINK" }, // GPIO Blink Enable
293 { 0x1c, 4, "GP_SER_BLINK" }, // GP Serial Blink
294 { 0x20, 4, "GP_SB_CMDSTS" }, // GP Serial Blink Command Status
295 { 0x24, 4, "GP_SB_DATA" }, // GP Serial Blink Data
296 { 0x28, 2, "GPI_NMI_EN" }, // GPI NMI Enable
297 { 0x2a, 2, "GPI_NMI_STS" }, // GPI NMI Status
298 { 0x2c, 4, "RESERVED" }, // Reserved
299 { 0x30, 4, "GPI_ROUT" }, // GPI Interrupt Input Route
300 { 0x34, 4, "RESERVED" }, // Reserved
301 { 0x38, 4, "RESERVED" }, // Reserved
302 { 0x3C, 4, "RESERVED" }, // Reserved
303 { 0x40, 4, "RESERVED" }, // Reserved
304 { 0x44, 4, "RESERVED" }, // Reserved
305 { 0x48, 4, "RESERVED" }, // Reserved
306 { 0x4C, 4, "RESERVED" }, // Reserved
307 { 0x50, 4, "ALT_GPI_SMI_STS" }, // Alternate GPI SMI Status
308 { 0x54, 4, "ALT_GPI_SMI_EN" }, // Alternate GPI SMI Enable
309 { 0x58, 4, "RESERVED" }, // Reserved
310 { 0x5C, 4, "RESERVED" }, // Reserved
311 { 0x60, 4, "GP_RST_SEL1" }, // GPIO Reset Select 1
312 { 0x64, 4, "GP_RST_SEL2" }, // GPIO Reset Select 2
313 { 0x68, 4, "GP_RST_SEL3" }, // GPIO Reset Select 3
314 { 0x6c, 4, "RESERVED" }, // Reserved
315 { 0x70, 4, "RESERVED" }, // Reserved
316 { 0x74, 4, "RESERVED" }, // Reserved
317 { 0x78, 4, "RESERVED" }, // Reserved
318 { 0x7c, 4, "GPIO_GC" }, // GPIO Global Configuration
319 { 0x80, 4, "GPI_IS[31:0]" }, // GPI Interrupt Status [31:0]
320 { 0x84, 4, "GPI_IS[63:32]" }, // GPI Interrupt Status [63:32]
321 { 0x88, 4, "GPI_IS[94:64]" }, // GPI Interrupt Status [94:64]
322 { 0x8C, 4, "RESERVED" }, // Reserved
323 { 0x90, 4, "GPI_IE[31:0]" }, // GPI Interrupt Enable [31:0]
324 { 0x94, 4, "GPI_IE[63:32]" }, // GPI Interrupt Enable [63:32]
325 { 0x98, 4, "GPI_IE[94:64]" }, // GPI Interrupt Enable [94:64]
326 { 0x9C, 4, "RESERVED" }, // Reserved
327 /* { 0x100, 4, "GPnCONFIGA" }, // GPIO Configuration A Register (n = 0) */
328 /* { 0x104, 4, "GPnCONFIGB" }, // GPIO Configuration B Register (n = 0) */
329 /* { ... } GPIO size = 95 */
330 /* { 0x3f0, 4, "GPnCONFIGA" }, // GPIO Configuration A Register (n = 94) */
331 /* { 0x3f4, 4, "GPnCONFIGB" }, // GPIO Configuration B Register (n = 94) */
332
333 };
334
335 /* Default values for Cougar Point desktop chipsets */
336 static const gpio_default_t cp_pch_desktop_defaults[] = {
337 { 0x00, 0xb96ba1ff },
338 { 0x04, 0xf6ff6eff },
339 { 0x0c, 0x02fe0100 },
340 { 0x18, 0x00040000 },
341 { 0x28, 0x00000000 },
342 { 0x2c, 0x00000000 },
343 { 0x30, 0x020300ff },
344 { 0x34, 0x1f57fff4 },
345 { 0x38, 0xa4aa0007 },
346 { 0x40, 0x00000130 },
347 { 0x44, 0x00000ff0 },
348 { 0x48, 0x000000c0 },
349 { 0x60, 0x01000000 },
350 { 0x64, 0x00000000 },
351 { 0x68, 0x00000000 },
352 };
353 /* Default values for Cougar Point mobile chipsets */
354 static const gpio_default_t cp_pch_mobile_defaults[] = {
355 { 0x00, 0xb96ba1ff },
356 { 0x04, 0xf6ff6eff },
357 { 0x0c, 0x02fe0100 },
358 { 0x18, 0x00040000 },
359 { 0x28, 0x00000000 },
360 { 0x2c, 0x00000000 },
361 { 0x30, 0x020300fe },
362 { 0x34, 0x1f57fff4 },
363 { 0x38, 0xa4aa0007 },
364 { 0x40, 0x00000030 },
365 { 0x44, 0x00000ff0 },
366 { 0x48, 0x000000c0 },
367 { 0x60, 0x01000000 },
368 { 0x64, 0x00000000 },
369 { 0x68, 0x00000000 },
370 };
371 /* Default values for Panther Point desktop chipsets */
372 static const gpio_default_t pp_pch_desktop_defaults[] = {
373 { 0x00, 0xb96ba1ff },
374 { 0x04, 0xeeff6eff },
375 { 0x0c, 0x02fe0100 },
376 { 0x18, 0x00040000 },
377 { 0x28, 0x00000000 },
378 { 0x2c, 0x00000000 },
379 { 0x30, 0x020300ff },
380 { 0x34, 0x1f57fff4 },
381 { 0x38, 0xa4aa0007 },
382 { 0x40, 0x00000130 },
383 { 0x44, 0x00000ff0 },
384 { 0x48, 0x000000c0 },
385 { 0x60, 0x01000000 },
386 { 0x64, 0x00000000 },
387 { 0x68, 0x00000000 },
388 };
389 /* Default values for Panther Point mobile chipsets */
390 static const gpio_default_t pp_pch_mobile_defaults[] = {
391 { 0x00, 0xb96ba1ff },
392 { 0x04, 0xeeff6eff },
393 { 0x0c, 0x02fe0100 },
394 { 0x18, 0x00040000 },
395 { 0x28, 0x00000000 },
396 { 0x2c, 0x00000000 },
397 { 0x30, 0x020300fe },
398 { 0x34, 0x1f57fff4 },
399 { 0x38, 0xa4aa0007 },
400 { 0x40, 0x00000030 },
401 { 0x44, 0x00000ff0 },
402 { 0x48, 0x000000c0 },
403 { 0x60, 0x01000000 },
404 { 0x64, 0x00000000 },
405 { 0x68, 0x00000000 },
406 };
407
408 /* Baytrail */
409 static const io_register_t baytrail_score_ssus_gpio_registers[] = {
410 { 0x00, 4, "SC_USE_SEL_31_0_" },
411 { 0x04, 4, "SC_IO_SEL_31_0_" },
412 { 0x08, 4, "SC_GP_LVL_31_0_)" },
413 { 0x0C, 4, "SC_TPE_31_0_" },
414 { 0x10, 4, "SC_TNE_31_0_" },
415 { 0x14, 4, "SC_TS_31_0_" },
416 { 0x20, 4, "SC_USE_SEL_63_32_" },
417 { 0x24, 4, "SC_IO_SEL_63_32_" },
418 { 0x28, 4, "SC_GP_LVL_63_32_" },
419 { 0x2C, 4, "SC_TPE_63_32_" },
420 { 0x30, 4, "SC_TNE_63_32_" },
421 { 0x34, 4, "SC_TS_63_32_" },
422 { 0x40, 4, "SC_USE_SEL_95_64_" },
423 { 0x44, 4, "SC_IO_SEL_95_64_" },
424 { 0x48, 4, "SC_GP_LVL_95_64_" },
425 { 0x4C, 4, "SC_TPE_95_64_" },
426 { 0x50, 4, "SC_TNE_95_64_" },
427 { 0x54, 4, "SC_TS_95_64_" },
428 { 0x58, 4, "SC_USE_SEL_127_96_" },
429 { 0x64, 4, "SC_IO_SEL_127_96_" },
430 { 0x68, 4, "SC_GP_LVL_127_96_" },
431 { 0x6C, 4, "SC_TPE_127_96_" },
432 { 0x70, 4, "SC_TNE_127_96_" },
433 { 0x74, 4, "SC_TS_127_96_" },
434
435 { 0x80 + 0x00, 4, "SUS_USE_SEL_31_0_" },
436 { 0x80 + 0x04, 4, "SUS_IO_SEL_31_0_" },
437 { 0x80 + 0x08, 4, "SUS_GP_LVL_31_0_" },
438 { 0x80 + 0x0c, 4, "SUS_TPE_31_0_" },
439 { 0x80 + 0x10, 4, "SUS_TNE_31_0_" },
440 { 0x80 + 0x14, 4, "SUS_TS_31_0_" },
441 { 0x80 + 0x18, 4, "SUS_WAKE_EN_31_0_" },
442 { 0x80 + 0x20, 4, "SUS_USE_SEL_43_32_" },
443 { 0x80 + 0x24, 4, "SUS_IO_SEL_43_32_" },
444 { 0x80 + 0x28, 4, "SUS_GP_LVL_43_32_" },
445 { 0x80 + 0x2c, 4, "SUS_TPE_43_32_" },
446 { 0x80 + 0x30, 4, "SUS_TNE_43_32_" },
447 { 0x80 + 0x34, 4, "SUS_TS_43_32_" },
448 { 0x80 + 0x38, 4, "SUS_WAKE_EN_43_32_" }
449 };
450
451 /* Description of GPIO 'bank' ex. {ncore, score. ssus} */
452 struct gpio_bank {
453 const uint32_t gpio_count;
454 const u8* gpio_to_pad;
455 const unsigned long pad_base_offset;
456 const char* gpio_name;
457 const char ** func_names;
458 };
459
460 /* Number of GPIOs in each bank */
461 #define BANK_COUNT 3
462 #define GPNCORE_COUNT 27
463 #define GPSCORE_COUNT 102
464 #define GPSSUS_COUNT 44
465
466 /* IO Memory offsets */
467 #define IO_BASE_OFFSET_GPNCORE 0x1000
468 #define IO_BASE_OFFSET_GPSCORE 0x0000
469 #define IO_BASE_OFFSET_GPSSUS 0x2000
470
471 static const char *ncore_func_names[GPNCORE_COUNT * 8] = {
472 "GPIO_S0_NC[00]", "RESERVED", "DDI0_HPD", "-", "-", "-", "-", "-",
473 "GPIO_S0_NC[01]", "-", "DDI0_DDCDATA", "-", "-", "-", "-", "-",
474 "GPIO_S0_NC[02]", "-", "DDI0_DDCCLK", "-", "-", "-", "-", "-",
475 "GPIO_S0_NC[03]", "-", "DDI0_VDDEN", "-", "-", "-", "-", "-",
476 "GPIO_S0_NC[04]", "-", "DDI0_BKLTEN", "-", "-", "-", "-", "-",
477 "GPIO_S0_NC[05]", "-", "DDI0_BKLTCTL", "-", "-", "-", "-", "-",
478 "GPIO_S0_NC[06]", "RESERVED", "DDI1_HPD", "-", "-", "-", "-", "-",
479 "GPIO_S0_NC[07]", "-", "DDI1_DDCDATA", "-", "-", "-", "-", "-",
480 "GPIO_S0_NC[08]", "-", "DDI1_DDCCLK", "-", "-", "-", "-", "-",
481 "GPIO_S0_NC[09]", "RESERVED", "DDI1_VDDEN", "-", "-", "-", "-", "-",
482 "GPIO_S0_NC[10]", "RESERVED", "DDI1_BKLTEN", "-", "-", "-", "-", "-",
483 "GPIO_S0_NC[11]", "RESERVED", "DDI1_BKLTCTL", "-", "-", "-", "-", "-",
484 "GPIO_S0_NC[12]", "RESERVED", "-", "-", "-", "-", "-", "-",
485 "GPIO_S0_NC[13]", "RESERVED", "-", "-", "-", "-", "-", "-",
486 "GPIO_S0_NC[14]", "RESERVED", "-", "-", "-", "-", "-", "-",
487 "GPIO_S0_NC[15]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
488 "GPIO_S0_NC[16]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
489 "GPIO_S0_NC[17]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
490 "GPIO_S0_NC[18]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
491 "GPIO_S0_NC[19]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
492 "GPIO_S0_NC[20]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
493 "GPIO_S0_NC[21]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
494 "GPIO_S0_NC[22]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
495 "GPIO_S0_NC[23]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
496 "GPIO_S0_NC[24]", "RESERVED", "-", "-", "-", "-", "-", "-",
497 "GPIO_S0_NC[25]", "RESERVED", "-", "-", "-", "-", "-", "-",
498 "GPIO_S0_NC[26]", "RESERVED", "-", "-", "-", "-", "-", "-",
499 };
500
501 static const char *score_func_names[GPSCORE_COUNT * 8] = {
502 "GPIO_S0_SC[000]", "SATA_GP[0]", "-", "-", "-", "-", "-", "-",
503 "GPIO_S0_SC[001]", "SATA_GP[1]", "SATA_DEVSLP[0]", "-", "-", "-", "-", "-",
504 "GPIO_S0_SC[002]", "SATA_LED#", "-", "-", "-", "-", "-", "-",
505 "GPIO_S0_SC[003]", "PCIE_CLKREQ[0]#", "-", "-", "-", "-", "-", "-",
506 "GPIO_S0_SC[004]", "PCIE_CLKREQ[1]#", "-", "-", "-", "-", "-", "-",
507 "GPIO_S0_SC[005]", "PCIE_CLKREQ[2]#", "-", "-", "-", "-", "-", "-",
508 "GPIO_S0_SC[006]", "PCIE_CLKREQ[3]#", "-", "-", "-", "-", "-", "-",
509 "GPIO_S0_SC[007]", "RESERVED", "SD3_WP", "-", "-", "-", "-", "-",
510 "GPIO_S0_SC[008]", "I2S0_CLK", "HDA_RST#", "-", "-", "-", "-", "-",
511 "GPIO_S0_SC[009]", "I2S0_FRM", "HDA_SYNC", "-", "-", "-", "-", "-",
512 "GPIO_S0_SC[010]", "I2S0_DATAOUT", "HDA_CLK", "-", "-", "-", "-", "-",
513 "GPIO_S0_SC[011]", "I2S0_DATAIN", "HDA_SDO", "-", "-", "-", "-", "-",
514 "GPIO_S0_SC[012]", "I2S1_CLK", "HDA_SDI[0]", "-", "-", "-", "-", "-",
515 "GPIO_S0_SC[013]", "I2S1_FRM", "HDA_SDI[1]", "-", "-", "-", "-", "-",
516 "GPIO_S0_SC[014]", "I2S1_DATAOUT", "RESERVED", "-", "-", "-", "-", "-",
517 "GPIO_S0_SC[015]", "I2S1_DATAIN", "RESERVED", "-", "-", "-", "-", "-",
518 "GPIO_S0_SC[016]", "MMC1_CLK", "-", "MMC1_45_CLK", "-", "-", "-", "-",
519 "GPIO_S0_SC[017]", "MMC1_D[0]", "-", "MMC1_45_D[0]", "-", "-", "-", "-",
520 "GPIO_S0_SC[018]", "MMC1_D[1]", "-", "MMC1_45_D[1]", "-", "-", "-", "-",
521 "GPIO_S0_SC[019]", "MMC1_D[2]", "-", "MMC1_45_D[2]", "-", "-", "-", "-",
522 "GPIO_S0_SC[020]", "MMC1_D[3]", "-", "MMC1_45_D[3]", "-", "-", "-", "-",
523 "GPIO_S0_SC[021]", "MMC1_D[4]", "-", "MMC1_45_D[4]", "-", "-", "-", "-",
524 "GPIO_S0_SC[022]", "MMC1_D[5]", "-", "MMC1_45_D[5]", "-", "-", "-", "-",
525 "GPIO_S0_SC[023]", "MMC1_D[6]", "-", "MMC1_45_D[6]", "-", "-", "-", "-",
526 "GPIO_S0_SC[024]", "MMC1_D[7]", "-", "MMC1_45_D[7]", "-", "-", "-", "-",
527 "GPIO_S0_SC[025]", "MMC1_CMD", "-", "MMC1_45_CMD", "-", "-", "-", "-",
528 "GPIO_S0_SC[026]", "MMC1_RST#", "SATA_DEVSLP[0]", "MMC1_45_RST#", "-", "-", "-", "-",
529 "GPIO_S0_SC[027]", "SD2_CLK", "-", "-", "-", "-", "-", "-",
530 "GPIO_S0_SC[028]", "SD2_D[0]", "-", "-", "-", "-", "-", "-",
531 "GPIO_S0_SC[029]", "SD2_D[1]", "-", "-", "-", "-", "-", "-",
532 "GPIO_S0_SC[030]", "SD2_D[2]", "-", "-", "-", "-", "-", "-",
533 "GPIO_S0_SC[031]", "SD2_D[3]_CD#", "-", "-", "-", "-", "-", "-",
534 "GPIO_S0_SC[032]", "SD2_CMD", "-", "-", "-", "-", "-", "-",
535 "GPIO_S0_SC[033]", "SD3_CLK", "-", "-", "-", "-", "-", "-",
536 "GPIO_S0_SC[034]", "SD3_D[0]", "-", "-", "-", "-", "-", "-",
537 "GPIO_S0_SC[035]", "SD3_D[1]", "-", "-", "-", "-", "-", "-",
538 "GPIO_S0_SC[036]", "SD3_D[2]", "-", "-", "-", "-", "-", "-",
539 "GPIO_S0_SC[037]", "SD3_D[3]", "-", "-", "-", "-", "-", "-",
540 "GPIO_S0_SC[038]", "SD3_CD#", "-", "-", "-", "-", "-", "-",
541 "GPIO_S0_SC[039]", "SD3_CMD", "-", "-", "-", "-", "-", "-",
542 "GPIO_S0_SC[040]", "SD3_1P8EN", "-", "-", "-", "-", "-", "-",
543 "GPIO_S0_SC[041]", "SD3_PWREN#", "-", "-", "-", "-", "-", "-",
544 "GPIO_S0_SC[042]", "ILB_LPC_AD[0]", "-", "-", "-", "-", "-", "-",
545 "GPIO_S0_SC[043]", "ILB_LPC_AD[1]", "-", "-", "-", "-", "-", "-",
546 "GPIO_S0_SC[044]", "ILB_LPC_AD[2]", "-", "-", "-", "-", "-", "-",
547 "GPIO_S0_SC[045]", "ILB_LPC_AD[3]", "-", "-", "-", "-", "-", "-",
548 "GPIO_S0_SC[046]", "ILB_LPC_FRAME#", "-", "-", "-", "-", "-", "-",
549 "GPIO_S0_SC[047]", "ILB_LPC_CLK[0]", "-", "-", "-", "-", "-", "-",
550 "GPIO_S0_SC[048]", "ILB_LPC_CLK[1]", "-", "-", "-", "-", "-", "-",
551 "GPIO_S0_SC[049]", "ILB_LPC_CLKRUN#", "-", "-", "-", "-", "-", "-",
552 "GPIO_S0_SC[050]", "ILB_LPC_SERIRQ", "-", "-", "-", "-", "-", "-",
553 "GPIO_S0_SC[051]", "PCU_SMB_DATA", "-", "-", "-", "-", "-", "-",
554 "GPIO_S0_SC[052]", "PCU_SMB_CLK", "-", "-", "-", "-", "-", "-",
555 "GPIO_S0_SC[053]", "PCU_SMB_ALERT#", "-", "-", "-", "-", "-", "-",
556 "GPIO_S0_SC[054]", "ILB_8254_SPKR", "RESERVED", "-", "-", "-", "-", "-",
557 "GPIO_S0_SC[055]", "RESERVED", "-", "-", "-", "-", "-", "-",
558 "GPIO_S0_SC[056]", "RESERVED", "-", "-", "-", "-", "-", "-",
559 "GPIO_S0_SC[057]", "PCU_UART_TXD", "-", "-", "-", "-", "-", "-",
560 "GPIO_S0_SC[058]", "RESERVED", "-", "-", "-", "-", "-", "-",
561 "GPIO_S0_SC[059]", "RESERVED", "-", "-", "-", "-", "-", "-",
562 "GPIO_S0_SC[060]", "RESERVED", "-", "-", "-", "-", "-", "-",
563 "GPIO_S0_SC[061]", "PCU_UART_RXD", "-", "-", "-", "-", "-", "-",
564 "GPIO_S0_SC[062]", "LPE_I2S2_CLK", "SATA_DEVSLP[1]", "RESERVED", "-", "-", "-", "-",
565 "GPIO_S0_SC[063]", "LPE_I2S2_FRM", "RESERVED", "-", "-", "-", "-", "-",
566 "GPIO_S0_SC[064]", "LPE_I2S2_DATAIN", "-", "-", "-", "-", "-", "-",
567 "GPIO_S0_SC[065]", "LPE_I2S2_DATAOUT", "-", "-", "-", "-", "-", "-",
568 "GPIO_S0_SC[066]", "SIO_SPI_CS#", "-", "-", "-", "-", "-", "-",
569 "GPIO_S0_SC[067]", "SIO_SPI_MISO", "-", "-", "-", "-", "-", "-",
570 "GPIO_S0_SC[068]", "SIO_SPI_MOSI", "-", "-", "-", "-", "-", "-",
571 "GPIO_S0_SC[069]", "SIO_SPI_CLK", "-", "-", "-", "-", "-", "-",
572 "GPIO_S0_SC[070]", "SIO_UART1_RXD", "RESERVED", "-", "-", "-", "-", "-",
573 "GPIO_S0_SC[071]", "SIO_UART1_TXD", "RESERVED", "-", "-", "-", "-", "-",
574 "GPIO_S0_SC[072]", "SIO_UART1_RTS#", "-", "-", "-", "-", "-", "-",
575 "GPIO_S0_SC[073]", "SIO_UART1_CTS#", "-", "-", "-", "-", "-", "-",
576 "GPIO_S0_SC[074]", "SIO_UART2_RXD", "-", "-", "-", "-", "-", "-",
577 "GPIO_S0_SC[075]", "SIO_UART2_TXD", "-", "-", "-", "-", "-", "-",
578 "GPIO_S0_SC[076]", "SIO_UART2_RTS#", "-", "-", "-", "-", "-", "-",
579 "GPIO_S0_SC[077]", "SIO_UART2_CTS#", "-", "-", "-", "-", "-", "-",
580 "GPIO_S0_SC[078]", "SIO_I2C0_DATA", "-", "-", "-", "-", "-", "-",
581 "GPIO_S0_SC[079]", "SIO_I2C0_CLK", "-", "-", "-", "-", "-", "-",
582 "GPIO_S0_SC[080]", "SIO_I2C1_DATA", "-", "-", "-", "-", "-", "-",
583 "GPIO_S0_SC[081]", "SIO_I2C1_CLK", "RESERVED", "-", "-", "-", "-", "-",
584 "GPIO_S0_SC[082]", "SIO_I2C2_DATA", "-", "-", "-", "-", "-", "-",
585 "GPIO_S0_SC[083]", "SIO_I2C2_CLK", "-", "-", "-", "-", "-", "-",
586 "GPIO_S0_SC[084]", "SIO_I2C3_DATA", "-", "-", "-", "-", "-", "-",
587 "GPIO_S0_SC[085]", "SIO_I2C3_CLK", "-", "-", "-", "-", "-", "-",
588 "GPIO_S0_SC[086]", "SIO_I2C4_DATA", "-", "-", "-", "-", "-", "-",
589 "GPIO_S0_SC[087]", "SIO_I2C4_CLK", "-", "-", "-", "-", "-", "-",
590 "GPIO_S0_SC[088]", "SIO_I2C5_DATA", "-", "-", "-", "-", "-", "-",
591 "GPIO_S0_SC[089]", "SIO_I2C5_CLK", "-", "-", "-", "-", "-", "-",
592 "GPIO_S0_SC[090]", "SIO_I2C6_DATA", "ILB_NMI", "-", "-", "-", "-", "-",
593 "GPIO_S0_SC[091]", "SIO_I2C6_CLK", "SD3_WP", "-", "-", "-", "-", "-",
594 "RESERVED", "GPIO_S0_SC[092]", "-", "-", "-", "-", "-", "-",
595 "RESERVED", "GPIO_S0_SC[093]", "-", "-", "-", "-", "-", "-",
596 "GPIO_S0_SC[094]", "SIO_PWM[0]", "-", "-", "-", "-", "-", "-",
597 "GPIO_S0_SC[095]", "SIO_PWM[1]", "-", "-", "-", "-", "-", "-",
598 "GPIO_S0_SC[096]", "PMC_PLT_CLK[0]", "-", "-", "-", "-", "-", "-",
599 "GPIO_S0_SC[097]", "PMC_PLT_CLK[1]", "-", "-", "-", "-", "-", "-",
600 "GPIO_S0_SC[098]", "PMC_PLT_CLK[2]", "-", "-", "-", "-", "-", "-",
601 "GPIO_S0_SC[099]", "PMC_PLT_CLK[3]", "-", "-", "-", "-", "-", "-",
602 "GPIO_S0_SC[100]", "PMC_PLT_CLK[4]", "-", "-", "-", "-", "-", "-",
603 "GPIO_S0_SC[101]", "PMC_PLT_CLK[5]", "-", "-", "-", "-", "-", "-",
604 };
605
606 static const char *ssus_func_names[GPSSUS_COUNT * 8] = {
607 "GPIO_S5[00]", "RESERVED", "-", "-", "-", "-", "-", "-",
608 "GPIO_S5[01]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[1]#", "-",
609 "GPIO_S5[02]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[2]#", "-",
610 "GPIO_S5[03]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[3]#", "-",
611 "GPIO_S5[04]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
612 "GPIO_S5[05]", "PMC_SUSCLK[1]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
613 "GPIO_S5[06]", "PMC_SUSCLK[2]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
614 "GPIO_S5[07]", "PMC_SUSCLK[3]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
615 "GPIO_S5[08]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
616 "GPIO_S5[09]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
617 "GPIO_S5[10]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "-", "-",
618 "PMC_SUSPWRDNACK", "GPIO_S5[11]", "-", "-", "-", "-", "-", "-",
619 "PMC_SUSCLK[0]", "GPIO_S5[12]", "-", "-", "-", "-", "-", "-",
620 "RESERVED", "GPIO_S5[13]", "-", "-", "-", "-", "-", "-",
621 "RESERVED", "GPIO_S5[14]", "USB_ULPI_RST#","-", "-", "-", "-", "-",
622 "PMC_WAKE_PCIE[0]#", "GPIO_S5[15]", "-", "-", "-", "-", "-", "-",
623 "PMC_PWRBTN#", "GPIO_S5[16]", "-", "-", "-", "-", "-", "-",
624 "RESERVED", "GPIO_S5[17]", "-", "-", "-", "-", "-", "-",
625 "PMC_SUS_STAT#", "GPIO_S5[18]", "-", "-", "-", "-", "-", "-",
626 "USB_OC[0]#", "GPIO_S5[19]", "-", "-", "-", "-", "-", "-",
627 "USB_OC[1]#", "GPIO_S5[20]", "-", "-", "-", "-", "-", "-",
628 "PCU_SPI_CS[1]#", "GPIO_S5[21]", "-", "-", "-", "-", "-", "-",
629 "GPIO_S5[22]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
630 "GPIO_S5[23]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
631 "GPIO_S5[24]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
632 "GPIO_S5[25]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
633 "GPIO_S5[26]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
634 "GPIO_S5[27]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
635 "GPIO_S5[28]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
636 "GPIO_S5[29]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
637 "GPIO_S5[30]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
638 "GPIO_S5[31]", "USB_ULPI_CLK", "RESERVED", "RESERVED", "-", "-", "-", "-",
639 "GPIO_S5[32]", "USB_ULPI_DATA[0]", "RESERVED", "RESERVED", "-", "-", "-", "-",
640 "GPIO_S5[33]", "USB_ULPI_DATA[1]", "RESERVED", "RESERVED", "-", "-", "-", "-",
641 "GPIO_S5[34]", "USB_ULPI_DATA[2]", "RESERVED", "RESERVED", "-", "-", "-", "-",
642 "GPIO_S5[35]", "USB_ULPI_DATA[3]", "RESERVED", "RESERVED", "-", "-", "-", "-",
643 "GPIO_S5[36]", "USB_ULPI_DATA[4]", "RESERVED", "RESERVED", "-", "-", "-", "-",
644 "GPIO_S5[37]", "USB_ULPI_DATA[5]", "RESERVED", "RESERVED", "-", "-", "-", "-",
645 "GPIO_S5[38]", "USB_ULPI_DATA[6]", "RESERVED", "RESERVED", "-", "-", "-", "-",
646 "GPIO_S5[39]", "USB_ULPI_DATA[7]", "RESERVED", "RESERVED", "-", "-", "-", "-",
647 "GPIO_S5[40]", "USB_ULPI_DIR", "RESERVED", "RESERVED", "-", "-", "-", "-",
648 "GPIO_S5[41]", "USB_ULPI_NXT", "RESERVED", "RESERVED", "-", "-", "-", "-",
649 "GPIO_S5[42]", "USB_ULPI_STP", "RESERVED", "RESERVED", "-", "-", "-", "-",
650 "GPIO_S5[43]", "USB_ULPI_REFCLK", "RESERVED", "RESERVED", "-", "-", "-", "-",
651 };
652
653 /* GPIO-to-Pad LUTs - Translate the GPIO number to the pad register */
654 static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
655 { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
656 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
657 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
658 2, 5, 9 }; /* [24:26] */
659
660 static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =
661 { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
662 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
663 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
664 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
665 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
666 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
667 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
668 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
669 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
670 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
671 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
672 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
673 106, 87, 91, 104, 97, 100 }; /* [96:101] */
674
675 static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
676 { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
677 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
678 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
679 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
680 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
681 52, 53, 59, 40 }; /* [40:43] */
682
683 static const struct gpio_bank gpio_banks[] = {
684 {
685 .gpio_count = GPNCORE_COUNT,
686 .gpio_to_pad = gpncore_gpio_to_pad,
687 .pad_base_offset = IO_BASE_OFFSET_GPNCORE,
688 .gpio_name = "NCORE GPIOs",
689 .func_names = ncore_func_names,
690 },
691 {
692 .gpio_count = GPSCORE_COUNT,
693 .gpio_to_pad = gpscore_gpio_to_pad,
694 .pad_base_offset = IO_BASE_OFFSET_GPSCORE,
695 .gpio_name = "SCORE GPIOs (GPIO_S0_SC_XX)",
696 .func_names = score_func_names,
697 },
698 {
699 .gpio_count = GPSSUS_COUNT,
700 .gpio_to_pad = gpssus_gpio_to_pad,
701 .pad_base_offset = IO_BASE_OFFSET_GPSSUS,
702 .gpio_name = "SSUS GPIOs (GPIO_S5)",
703 .func_names = ssus_func_names,
704 },
705 };
706
707 const char *pull_assignment[] = {"None","Up ","Down","Res "};
708 const char *pull_strength[] = {"2k", "10k", "20k", "40k"};
709
710 static int show_baytrail_pad_reg(struct pci_dev *sb){
711
712 uint64_t iobase = (uint64_t)pci_read_long(sb, 0x4c) & 0xffffc000;
713 uint32_t val, bank, gpio, offset, size = 0x3000;
714 volatile uint32_t *reg;
715
716 reg = map_physical(iobase, size);
717
718 if (reg == NULL) {
719 perror("Error mapping IOBASE");
720 return 1;
721 }
722
723 printf("\nIOBASE: 0x%08lx\n",(long int)iobase);
724
725 /* Display function values */
726 for (bank = 0; bank < BANK_COUNT; bank++) {
727 printf("\n========== Bay Trail %s ===========\n\n",
728 gpio_banks[bank].gpio_name);
729
730 printf("Address | GPIO # | reg value | "
731 "Pull Dir & Str | Func #: Func Name |"
732 " I/O | Current Val\n");
733
734 for (gpio=0; gpio < gpio_banks[bank].gpio_count; gpio++) {
735 offset = gpio_banks[bank].pad_base_offset +
736 (16 * gpio_banks[bank].gpio_to_pad[gpio]);
737
738 /* Read Pad Configuration 0 Register */
739 val = *(reg + offset / 4);
740 printf("iobase + 0x%04x | GPIO %3d | ",offset, gpio);
741 printf("0x%08x | ", val);
742 printf("Pull: %4s %3s | ",pull_assignment[(val >> 7) & 3],
743 ((val >> 7) & 3) ?
744 pull_strength[(val >> 9) & 3] :
745 "");
746 printf("Func %d",val & 0x07);
747 if (gpio_banks[bank].func_names != NULL)
748 printf(": %-20s | ", gpio_banks[bank].func_names[(gpio * 8) + (val & 0x07)] );
749
750 /* Read the Pad Value Register */
751 val = *(reg + offset / 4 + 2);
752 printf("%6s%3s%5s | %-4s",
753 (val & 0x02) ? "" : "Output",
754 (val & 0x06) ? "" : " / ",
755 (val & 0x04) ? "" : "Input",
756 (val & 0x01) ? "High" : "Low");
757 printf("\n");
758 }
759 }
760
761 unmap_physical((void *)reg, size);
762 return 0;
763 }
764
765 static uint16_t gpiobase;
766
767 static void print_reg(const io_register_t *const reg)
768 {
769 switch (reg->size) {
770 case 4:
771 printf("gpiobase+0x%04x: 0x%08x (%s)\n",
772 reg->addr, inl(gpiobase+reg->addr), reg->name);
773 break;
774 case 2:
775 printf("gpiobase+0x%04x: 0x%04x (%s)\n",
776 reg->addr, inw(gpiobase+reg->addr), reg->name);
777 break;
778 case 1:
779 printf("gpiobase+0x%04x: 0x%02x (%s)\n",
780 reg->addr, inb(gpiobase+reg->addr), reg->name);
781 break;
782 }
783 }
784
785 static uint32_t get_diff(const io_register_t *const reg, const uint32_t def)
786 {
787 uint32_t gpio_diff = 0;
788 switch (reg->size) {
789 case 4:
790 gpio_diff = def ^ inl(gpiobase+reg->addr);
791 break;
792 case 2:
793 gpio_diff = (uint16_t)def ^ inw(gpiobase+reg->addr);
794 break;
795 case 1:
796 gpio_diff = (uint8_t)def ^ inb(gpiobase+reg->addr);
797 break;
798 }
799 return gpio_diff;
800 }
801
802 static void print_diff(const io_register_t *const reg,
803 const uint32_t def, const uint32_t diff)
804 {
805 switch (reg->size) {
806 case 4:
807 printf("gpiobase+0x%04x: 0x%08x (%s) DEFAULT\n",
808 reg->addr, def, reg->name);
809 printf("gpiobase+0x%04x: 0x%08x (%s) DIFF\n",
810 reg->addr, diff, reg->name);
811 break;
812 case 2:
813 printf("gpiobase+0x%04x: 0x%04x (%s) DEFAULT\n",
814 reg->addr, def, reg->name);
815 printf("gpiobase+0x%04x: 0x%04x (%s) DIFF\n",
816 reg->addr, diff, reg->name);
817 break;
818 case 1:
819 printf("gpiobase+0x%04x: 0x%02x (%s) DEFAULT\n",
820 reg->addr, def, reg->name);
821 printf("gpiobase+0x%04x: 0x%02x (%s) DIFF\n",
822 reg->addr, diff, reg->name);
823 break;
824 }
825 }
826
827 int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
828 {
829 int i, j, size, defaults_size = 0;
830 const io_register_t *gpio_registers;
831 const gpio_default_t *gpio_defaults = NULL;
832 uint32_t gpio_diff;
833
834 switch (sb->device_id) {
835 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
836 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
837 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
838 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
839 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
840 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
841 gpio_registers = lynxpoint_lp_gpio_registers;
842 size = ARRAY_SIZE(lynxpoint_lp_gpio_registers);
843 break;
844 case PCI_DEVICE_ID_INTEL_C8_MOBILE:
845 case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
846 case PCI_DEVICE_ID_INTEL_Z87:
847 case PCI_DEVICE_ID_INTEL_Z85:
848 case PCI_DEVICE_ID_INTEL_HM86:
849 case PCI_DEVICE_ID_INTEL_H87:
850 case PCI_DEVICE_ID_INTEL_HM87:
851 case PCI_DEVICE_ID_INTEL_Q85:
852 case PCI_DEVICE_ID_INTEL_Q87:
853 case PCI_DEVICE_ID_INTEL_QM87:
854 case PCI_DEVICE_ID_INTEL_B85:
855 case PCI_DEVICE_ID_INTEL_C222:
856 case PCI_DEVICE_ID_INTEL_C224:
857 case PCI_DEVICE_ID_INTEL_C226:
858 case PCI_DEVICE_ID_INTEL_H81:
859 case PCI_DEVICE_ID_INTEL_C9_MOBILE:
860 case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
861 case PCI_DEVICE_ID_INTEL_HM97:
862 case PCI_DEVICE_ID_INTEL_Z97:
863 case PCI_DEVICE_ID_INTEL_H97:
864 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
865 gpio_registers = pch_gpio_registers;
866 size = ARRAY_SIZE(pch_gpio_registers);
867 break;
868 case PCI_DEVICE_ID_INTEL_3400:
869 case PCI_DEVICE_ID_INTEL_3420:
870 case PCI_DEVICE_ID_INTEL_3450:
871 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
872 case PCI_DEVICE_ID_INTEL_B55_A:
873 case PCI_DEVICE_ID_INTEL_B55_B:
874 case PCI_DEVICE_ID_INTEL_H55:
875 case PCI_DEVICE_ID_INTEL_H57:
876 case PCI_DEVICE_ID_INTEL_P55:
877 case PCI_DEVICE_ID_INTEL_Q57:
878 gpiobase = pci_read_word(sb, 0x48) & 0xff80;
879 gpio_registers = pch_gpio_registers;
880 size = ARRAY_SIZE(pch_gpio_registers);
881 gpio_defaults = ip_pch_desktop_defaults;
882 defaults_size = ARRAY_SIZE(ip_pch_desktop_defaults);
883 break;
884 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
885 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
886 case PCI_DEVICE_ID_INTEL_HM55:
887 case PCI_DEVICE_ID_INTEL_HM57:
888 case PCI_DEVICE_ID_INTEL_PM55:
889 case PCI_DEVICE_ID_INTEL_QM57:
890 case PCI_DEVICE_ID_INTEL_QS57:
891 gpiobase = pci_read_word(sb, 0x48) & 0xff80;
892 gpio_registers = pch_gpio_registers;
893 size = ARRAY_SIZE(pch_gpio_registers);
894 gpio_defaults = ip_pch_mobile_defaults;
895 defaults_size = ARRAY_SIZE(ip_pch_mobile_defaults);
896 break;
897 case PCI_DEVICE_ID_INTEL_Z68:
898 case PCI_DEVICE_ID_INTEL_P67:
899 case PCI_DEVICE_ID_INTEL_H67:
900 case PCI_DEVICE_ID_INTEL_Q65:
901 case PCI_DEVICE_ID_INTEL_QS67:
902 case PCI_DEVICE_ID_INTEL_Q67:
903 case PCI_DEVICE_ID_INTEL_B65:
904 case PCI_DEVICE_ID_INTEL_C202:
905 case PCI_DEVICE_ID_INTEL_C204:
906 case PCI_DEVICE_ID_INTEL_C206:
907 case PCI_DEVICE_ID_INTEL_H61:
908 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
909 gpio_registers = pch_gpio_registers;
910 size = ARRAY_SIZE(pch_gpio_registers);
911 gpio_defaults = cp_pch_desktop_defaults;
912 defaults_size = ARRAY_SIZE(cp_pch_desktop_defaults);
913 break;
914 case PCI_DEVICE_ID_INTEL_UM67:
915 case PCI_DEVICE_ID_INTEL_HM65:
916 case PCI_DEVICE_ID_INTEL_HM67:
917 case PCI_DEVICE_ID_INTEL_QM67:
918 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
919 gpio_registers = pch_gpio_registers;
920 size = ARRAY_SIZE(pch_gpio_registers);
921 gpio_defaults = cp_pch_mobile_defaults;
922 defaults_size = ARRAY_SIZE(cp_pch_mobile_defaults);
923 break;
924 case PCI_DEVICE_ID_INTEL_Z77:
925 case PCI_DEVICE_ID_INTEL_Z75:
926 case PCI_DEVICE_ID_INTEL_Q77:
927 case PCI_DEVICE_ID_INTEL_Q75:
928 case PCI_DEVICE_ID_INTEL_B75:
929 case PCI_DEVICE_ID_INTEL_H77:
930 case PCI_DEVICE_ID_INTEL_C216:
931 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
932 gpio_registers = pch_gpio_registers;
933 size = ARRAY_SIZE(pch_gpio_registers);
934 gpio_defaults = pp_pch_desktop_defaults;
935 defaults_size = ARRAY_SIZE(pp_pch_desktop_defaults);
936 break;
937 case PCI_DEVICE_ID_INTEL_QM77:
938 case PCI_DEVICE_ID_INTEL_QS77:
939 case PCI_DEVICE_ID_INTEL_HM77:
940 case PCI_DEVICE_ID_INTEL_UM77:
941 case PCI_DEVICE_ID_INTEL_HM76:
942 case PCI_DEVICE_ID_INTEL_HM75:
943 case PCI_DEVICE_ID_INTEL_HM70:
944 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
945 gpio_registers = pch_gpio_registers;
946 size = ARRAY_SIZE(pch_gpio_registers);
947 gpio_defaults = pp_pch_mobile_defaults;
948 defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults);
949 break;
950 case PCI_DEVICE_ID_INTEL_ICH10:
951 case PCI_DEVICE_ID_INTEL_ICH10D:
952 case PCI_DEVICE_ID_INTEL_ICH10DO:
953 case PCI_DEVICE_ID_INTEL_ICH10R:
954 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
955 gpio_registers = ich10_gpio_registers;
956 size = ARRAY_SIZE(ich10_gpio_registers);
957 break;
958 case PCI_DEVICE_ID_INTEL_ICH9DH:
959 case PCI_DEVICE_ID_INTEL_ICH9DO:
960 case PCI_DEVICE_ID_INTEL_ICH9R:
961 case PCI_DEVICE_ID_INTEL_ICH9:
962 case PCI_DEVICE_ID_INTEL_ICH9M:
963 case PCI_DEVICE_ID_INTEL_ICH9ME:
964 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
965 gpio_registers = ich9_gpio_registers;
966 size = ARRAY_SIZE(ich9_gpio_registers);
967 break;
968 case PCI_DEVICE_ID_INTEL_ICH8:
969 case PCI_DEVICE_ID_INTEL_ICH8M:
970 case PCI_DEVICE_ID_INTEL_ICH8ME:
971 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
972 gpio_registers = ich8_gpio_registers;
973 size = ARRAY_SIZE(ich8_gpio_registers);
974 break;
975 case PCI_DEVICE_ID_INTEL_ICH7:
976 case PCI_DEVICE_ID_INTEL_ICH7M:
977 case PCI_DEVICE_ID_INTEL_ICH7DH:
978 case PCI_DEVICE_ID_INTEL_ICH7MDH:
979 case PCI_DEVICE_ID_INTEL_NM10:
980 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
981 gpio_registers = ich7_gpio_registers;
982 size = ARRAY_SIZE(ich7_gpio_registers);
983 break;
984 case PCI_DEVICE_ID_INTEL_ICH6:
985 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
986 gpio_registers = ich6_gpio_registers;
987 size = ARRAY_SIZE(ich6_gpio_registers);
988 break;
989 case PCI_DEVICE_ID_INTEL_ICH5:
990 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
991 gpio_registers = ich5_gpio_registers;
992 size = ARRAY_SIZE(ich5_gpio_registers);
993 break;
994 case PCI_DEVICE_ID_INTEL_ICH4:
995 case PCI_DEVICE_ID_INTEL_ICH4M:
996 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
997 gpio_registers = ich4_gpio_registers;
998 size = ARRAY_SIZE(ich4_gpio_registers);
999 break;
1000 case PCI_DEVICE_ID_INTEL_ICH2:
1001 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
1002 gpio_registers = ich2_gpio_registers;
1003 size = ARRAY_SIZE(ich2_gpio_registers);
1004 break;
1005 case PCI_DEVICE_ID_INTEL_ICH:
1006 case PCI_DEVICE_ID_INTEL_ICH0:
1007 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
1008 gpio_registers = ich0_gpio_registers;
1009 size = ARRAY_SIZE(ich0_gpio_registers);
1010 break;
1011
1012 case PCI_DEVICE_ID_INTEL_I63XX:
1013 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
1014 gpio_registers = i631x_gpio_registers;
1015 size = ARRAY_SIZE(i631x_gpio_registers);
1016 break;
1017 case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
1018 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
1019 gpio_registers = baytrail_score_ssus_gpio_registers;
1020 size = ARRAY_SIZE(baytrail_score_ssus_gpio_registers);
1021 break;
1022 case PCI_DEVICE_ID_INTEL_H110:
1023 case PCI_DEVICE_ID_INTEL_H170:
1024 case PCI_DEVICE_ID_INTEL_Z170:
1025 case PCI_DEVICE_ID_INTEL_Q170:
1026 case PCI_DEVICE_ID_INTEL_Q150:
1027 case PCI_DEVICE_ID_INTEL_B150:
1028 case PCI_DEVICE_ID_INTEL_C236:
1029 case PCI_DEVICE_ID_INTEL_C232:
1030 case PCI_DEVICE_ID_INTEL_QM170:
1031 case PCI_DEVICE_ID_INTEL_HM170:
1032 case PCI_DEVICE_ID_INTEL_CM236:
1033 case PCI_DEVICE_ID_INTEL_APL_LPC:
1034 case PCI_DEVICE_ID_INTEL_GLK_LPC:
1035 case PCI_DEVICE_ID_INTEL_DNV_LPC:
1036 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
1037 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
1038 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
1039 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
1040 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
1041 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
1042 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
1043 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
1044 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
1045 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
1046 case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
1047 case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
1048 case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
1049 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_SUPER:
1050 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_PREM:
1051 case PCI_DEVICE_ID_INTEL_TIGERPOINT_U_BASE:
1052 case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_SUPER:
1053 case PCI_DEVICE_ID_INTEL_TIGERPOINT_Y_PREM:
1054 case PCI_DEVICE_ID_INTEL_C621:
1055 case PCI_DEVICE_ID_INTEL_C622:
1056 case PCI_DEVICE_ID_INTEL_C624:
1057 case PCI_DEVICE_ID_INTEL_C625:
1058 case PCI_DEVICE_ID_INTEL_C626:
1059 case PCI_DEVICE_ID_INTEL_C627:
1060 case PCI_DEVICE_ID_INTEL_C628:
1061 case PCI_DEVICE_ID_INTEL_C629:
1062 case PCI_DEVICE_ID_INTEL_C621A:
1063 case PCI_DEVICE_ID_INTEL_C627A:
1064 case PCI_DEVICE_ID_INTEL_C629A:
1065 case PCI_DEVICE_ID_INTEL_C624_SUPER:
1066 case PCI_DEVICE_ID_INTEL_C627_SUPER_1:
1067 case PCI_DEVICE_ID_INTEL_C621_SUPER:
1068 case PCI_DEVICE_ID_INTEL_C627_SUPER_2:
1069 case PCI_DEVICE_ID_INTEL_C628_SUPER:
1070 case PCI_DEVICE_ID_INTEL_C621A_SUPER:
1071 case PCI_DEVICE_ID_INTEL_C627A_SUPER:
1072 case PCI_DEVICE_ID_INTEL_C629A_SUPER:
1073 case PCI_DEVICE_ID_INTEL_H270:
1074 case PCI_DEVICE_ID_INTEL_Z270:
1075 case PCI_DEVICE_ID_INTEL_Q270:
1076 case PCI_DEVICE_ID_INTEL_Q250:
1077 case PCI_DEVICE_ID_INTEL_B250:
1078 case PCI_DEVICE_ID_INTEL_Z370:
1079 case PCI_DEVICE_ID_INTEL_H310C:
1080 case PCI_DEVICE_ID_INTEL_X299:
1081 case PCI_DEVICE_ID_INTEL_H310:
1082 case PCI_DEVICE_ID_INTEL_H370:
1083 case PCI_DEVICE_ID_INTEL_Z390:
1084 case PCI_DEVICE_ID_INTEL_Q370:
1085 case PCI_DEVICE_ID_INTEL_B360:
1086 case PCI_DEVICE_ID_INTEL_C246:
1087 case PCI_DEVICE_ID_INTEL_C242:
1088 case PCI_DEVICE_ID_INTEL_QM370:
1089 case PCI_DEVICE_ID_INTEL_HM370:
1090 case PCI_DEVICE_ID_INTEL_CM246:
1091 case PCI_DEVICE_ID_INTEL_Q570:
1092 case PCI_DEVICE_ID_INTEL_Z590:
1093 case PCI_DEVICE_ID_INTEL_H570:
1094 case PCI_DEVICE_ID_INTEL_B560:
1095 case PCI_DEVICE_ID_INTEL_H510:
1096 case PCI_DEVICE_ID_INTEL_WM590:
1097 case PCI_DEVICE_ID_INTEL_QM580:
1098 case PCI_DEVICE_ID_INTEL_HM570:
1099 case PCI_DEVICE_ID_INTEL_C252:
1100 case PCI_DEVICE_ID_INTEL_C256:
1101 case PCI_DEVICE_ID_INTEL_W580:
1102 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
1103 case PCI_DEVICE_ID_INTEL_H610E:
1104 case PCI_DEVICE_ID_INTEL_Q670E:
1105 case PCI_DEVICE_ID_INTEL_R680E:
1106 case PCI_DEVICE_ID_INTEL_H610:
1107 case PCI_DEVICE_ID_INTEL_B660:
1108 case PCI_DEVICE_ID_INTEL_H670:
1109 case PCI_DEVICE_ID_INTEL_Q670:
1110 case PCI_DEVICE_ID_INTEL_Z690:
1111 case PCI_DEVICE_ID_INTEL_W680:
1112 case PCI_DEVICE_ID_INTEL_WM690:
1113 case PCI_DEVICE_ID_INTEL_HM670:
1114 case PCI_DEVICE_ID_INTEL_W790:
1115 case PCI_DEVICE_ID_INTEL_Z790:
1116 case PCI_DEVICE_ID_INTEL_H770:
1117 case PCI_DEVICE_ID_INTEL_B760:
1118 case PCI_DEVICE_ID_INTEL_HM770:
1119 case PCI_DEVICE_ID_INTEL_WM790:
1120 case PCI_DEVICE_ID_INTEL_C262:
1121 case PCI_DEVICE_ID_INTEL_C266:
1122 case PCI_DEVICE_ID_INTEL_ADL_P:
1123 case PCI_DEVICE_ID_INTEL_ADL_M:
1124 case PCI_DEVICE_ID_INTEL_ADL_N:
1125 case PCI_DEVICE_ID_INTEL_RPL_P:
1126 case PCI_DEVICE_ID_INTEL_JSL:
1127 case PCI_DEVICE_ID_INTEL_EHL:
1128 case PCI_DEVICE_ID_INTEL_EBG:
1129 case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_M:
1130 case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_1:
1131 case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_2:
1132 case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_3:
1133 case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_4:
1134 case PCI_DEVICE_ID_INTEL_CORE_MTL_ID_P_5:
1135 case PCI_DEVICE_ID_INTEL_MTL_0:
1136 case PCI_DEVICE_ID_INTEL_MTL_1:
1137 case PCI_DEVICE_ID_INTEL_MTL_2:
1138 case PCI_DEVICE_ID_INTEL_MTL_3:
1139 case PCI_DEVICE_ID_INTEL_MTL_4:
1140 case PCI_DEVICE_ID_INTEL_MTL_5:
1141 case PCI_DEVICE_ID_INTEL_MTL_6:
1142 case PCI_DEVICE_ID_INTEL_MTL_7:
1143 print_gpio_groups(sb);
1144 return 0;
1145 case PCI_DEVICE_ID_INTEL_82371XX:
1146 printf("This southbridge has GPIOs in the PM unit.\n");
1147 return 1;
1148 default:
1149 printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
1150 return 1;
1151 }
1152
1153 if (show_diffs && !show_all)
1154 printf("\n========== GPIO DIFFS ===========\n\n");
1155 else
1156 printf("\n============= GPIOS =============\n\n");
1157
1158 printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
1159
1160 j = 0;
1161 for (i = 0; i < size; i++) {
1162 if (show_all)
1163 print_reg(&gpio_registers[i]);
1164
1165 if (show_diffs &&
1166 (j < defaults_size) &&
1167 (gpio_defaults[j].addr == gpio_registers[i].addr)) {
1168 gpio_diff = get_diff(&gpio_registers[i],
1169 gpio_defaults[j].def);
1170 if (gpio_diff) {
1171 if (!show_all)
1172 print_reg(&gpio_registers[i]);
1173 print_diff(&gpio_registers[i],
1174 gpio_defaults[j].def, gpio_diff);
1175 if (!show_all)
1176 printf("\n");
1177 }
1178 j++;
1179 }
1180 }
1181
1182 switch (sb->device_id) {
1183 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
1184 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
1185 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
1186 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
1187 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
1188 for (i = 0; i < 95; i++) {
1189 io_register_t tmp_gpio;
1190 char gpio_name[32];
1191 uint16_t tmp_addr = 0x100 + (4 * i * 2);
1192
1193 snprintf(gpio_name, sizeof(gpio_name), "GP%dCONFIGA", i);
1194 tmp_gpio.addr = tmp_addr;
1195 tmp_gpio.name = gpio_name;
1196 tmp_gpio.size = 4;
1197
1198 if (show_all)
1199 print_reg(&tmp_gpio);
1200
1201 snprintf(gpio_name, 32, "GP%dCONFIGB", i);
1202 tmp_gpio.addr = tmp_addr + 4;
1203 tmp_gpio.name = gpio_name;
1204 tmp_gpio.size = 4;
1205
1206 if (show_all)
1207 print_reg(&tmp_gpio);
1208 }
1209 break;
1210 case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
1211 show_baytrail_pad_reg(sb);
1212 break;
1213 default:
1214 break;
1215 }
1216
1217 return 0;
1218 }
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