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soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / util / inteltool / spi.c
blobcba43ed10e918a3a7add657d2c85f8901b805577
1
2 #include <stdio.h>
3 #include <stdlib.h>
4 #include "inteltool.h"
5
6 static const io_register_t ich6_bios_cntl_registers[] = {
7 { 0x0, 1, "BIOSWE - write enable" },
8 { 0x1, 1, "BLE - lock enable" },
9 { 0x2, 6, "reserved" },
10 };
11
12 static const io_register_t ich7_bios_cntl_registers[] = {
13 { 0x0, 1, "BIOSWE - write enable" },
14 { 0x1, 1, "BLE - lock enable" },
15 { 0x2, 2, "SPI Read configuration" },
16 { 0x4, 1, "TopSwapStatus" },
17 { 0x5, 3, "reserved" },
18 };
19
20 static const io_register_t pch_bios_cntl_registers[] = {
21 { 0x0, 1, "BIOSWE - write enable" },
22 { 0x1, 1, "BLE - lock enable" },
23 { 0x2, 2, "SPI Read configuration" },
24 { 0x4, 1, "TopSwapStatus" },
25 { 0x5, 1, "SMM BIOS Write Protect Disable" },
26 { 0x6, 2, "reserved" },
27 };
28
29 static const io_register_t adl_pch_bios_cntl_registers[] = {
30 { 0x0, 1, "WPD - Write Protect Disable" },
31 { 0x1, 1, "LE - Lock Enable" },
32 { 0x2, 1, "ESPI - eSPI Enable Pin Strap" },
33 { 0x3, 1, "Reserved" },
34 { 0x4, 1, "TS - Top Swap" },
35 { 0x5, 1, "EISS - Enable InSMM.STS" },
36 { 0x6, 1, "BBS - Boot BIOS Strap" },
37 { 0x7, 1, "BILD - BIOS Interface Lock-Down" },
38 { 0x8, 1, "BWPDS - BIOS Write Protect Disable Status" },
39 { 0x9, 1, "Reserved" },
40 { 0x10, 1, "BWRS - BIOS Write Status" },
41 { 0x11, 1, "BWRE - BIOS Write Reporting (Async-SMI)" },
42 { 0x12, 19, "Reserved" },
43 };
44
45 static const io_register_t elkhart_bios_cntl_registers[] = {
46 { 0x0, 1, "BIOSWE - write enable" },
47 { 0x1, 1, "BLE - lock enable" },
48 { 0x2, 1, "ESPI - eSPI Enable Pin Strap" },
49 { 0x3, 1, "Reserved" },
50 { 0x4, 1, "TS - TopSwapStatus" },
51 { 0x5, 1, "EISS - Enable InSMM.STS" },
52 { 0x6, 1, "BBS - Boot BIOS Strap" },
53 { 0x7, 1, "BILD - BIOS Interface Lock-Down" },
54 { 0x8, 1, "BWPDS - BIOS Write Protect Disable Status" },
55 { 0x9, 1, "Reserved" },
56 { 0xa, 1, "BWRS - BIOS Write Status" },
57 { 0xb, 1, "BWRE - BIOS Write Reporting (Async-SMI) Enable" },
58 };
59
60 #define ICH9_SPIBAR 0x3800
61 #define ICH78_SPIBAR 0x3020
62
63 static const io_register_t spi_bar_registers[] = {
64 { 0x00, 4, "BFPR - BIOS Flash primary region" },
65 { 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
66 { 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
67 { 0x08, 4, "FADDR - Flash Address" },
68 { 0x0c, 4, "Reserved" },
69 { 0x10, 4, "FDATA0" },
70 /* 0x10 .. 0x4f are filled with data */
71 { 0x50, 4, "FRACC - Flash Region Access Permissions" },
72 { 0x54, 4, "Flash Region 0" },
73 { 0x58, 4, "Flash Region 1" },
74 { 0x5c, 4, "Flash Region 2" },
75 { 0x60, 4, "Flash Region 3" },
76 { 0x64, 4, "Flash Region 4" },
77 { 0x74, 4, "FPR0 Flash Protected Range 0" },
78 { 0x78, 4, "FPR0 Flash Protected Range 1" },
79 { 0x7c, 4, "FPR0 Flash Protected Range 2" },
80 { 0x80, 4, "FPR0 Flash Protected Range 3" },
81 { 0x84, 4, "FPR0 Flash Protected Range 4" },
82 { 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
83 { 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
84 { 0x94, 2, "PREOP - Prefix opcode Configuration" },
85 { 0x96, 2, "OPTYPE - Opcode Type Configuration" },
86 { 0x98, 8, "OPMENU - Opcode Menu Configuration" },
87 { 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
88 { 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
89 { 0xb8, 4, "Reserved" },
90 { 0xc0, 4, "AFC - Additional Flash Control" },
91 { 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
92 { 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
93 { 0xd0, 4, "FPB - Flash Partition Boundary" },
94 };
95
96 static const io_register_t ich7_spi_bar_registers[] = {
97 { 0x00, 2, "SPIS - SPI Status" },
98 { 0x02, 2, "SPIC - SPI Control" },
99 { 0x04, 4, "SPIA - SPI Address" },
100 /*
101 *0x08 .. 0x47 are filled with data
102 *0x48 .. 0x4f is not mentioned by datasheet
103 */
104 { 0x50, 4, "BBAR - BIOS Base Address Configuration" },
105 { 0x54, 2, "PREOP Prefix Opcode Configuration" },
106 { 0x56, 2, "OPTYPE Opcode Type Configuration" },
107 { 0x58, 8, "OPMENU Opcode Menu Configuration" },
108 { 0x60, 4, "PBR0 Protected BIOS Range 0" },
109 { 0x64, 4, "PBR1 Protected BIOS Range 1" },
110 { 0x68, 4, "PBR2 Protected BIOS Range 2" },
111 };
112
113 /*
114 * Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series Processors for IoT Applications
115 * February 2023,
116 * Document number 636722
117 */
118 static const io_register_t elkhart_spi_bar_registers[] = {
119 { 0x00, 4, "BFPR - BIOS Flash primary region" },
120 { 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
121 { 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
122 { 0x08, 4, "FADDR - Flash Address" },
123 { 0x0c, 4, "BIOS_DLOCK - Discrete Lock Bits" },
124 { 0x10, 4, "FDATA0" },
125 /* 0x10 .. 0x4f are filled with data */
126 { 0x50, 4, "FRACC - Flash Region Access Permissions" },
127 { 0x54, 4, "Flash Region 0" },
128 { 0x58, 4, "Flash Region 1" },
129 { 0x5c, 4, "Flash Region 2" },
130 { 0x60, 4, "Flash Region 3" },
131 { 0x64, 4, "Flash Region 4" },
132 { 0x68, 4, "Flash Region 5" },
133 { 0x6c, 4, "Flash Region 6" },
134 { 0x70, 4, "Flash Region 7" },
135 { 0x74, 4, "Flash Region 8" },
136 { 0x78, 4, "Flash Region 9" },
137 { 0x7c, 4, "Flash Region 10" },
138 { 0x80, 4, "Flash Region 11" },
139 { 0x84, 4, "FPR0 - Flash Protected Range 0" },
140 { 0x88, 4, "FPR0 - Flash Protected Range 1" },
141 { 0x8c, 4, "FPR0 - Flash Protected Range 2" },
142 { 0x90, 4, "FPR0 - Flash Protected Range 3" },
143 { 0x94, 4, "FPR0 - Flash Protected Range 4" },
144 { 0x98, 4, "GPR0 - Global Protected Range 0" },
145 { 0xa0, 4, "SSFSTS - Software Sequencing Flash Status" },
146 { 0xa4, 2, "PREOP - Prefix opcode Configuration" },
147 { 0xa6, 2, "OPTYPE - Opcode Type Configuration" },
148 { 0xa8, 4, "OPMENU0 - Opcode Menu Configuration" },
149 { 0xac, 4, "OPMENU1 - Opcode Menu Configuration" },
150 { 0xb0, 4, "SFRACC - Secondary Flash Region Access Permissions" },
151 { 0xb4, 4, "FDOC - Flash Descriptor Observability Control" },
152 { 0xb8, 4, "FDOD - Flash Descriptor Observability Data" },
153 { 0xc0, 4, "AFC - Additional Flash Control" },
154 { 0xc4, 4, "SFDP0_VSCC0 - Vendor Specific Component Capabilities" },
155 { 0xc8, 4, "SFDP0_VSCC1 - Vendor Specific Component Capabilities" },
156 { 0xcc, 4, "PTINX - Parameter Table Index" },
157 { 0xd0, 4, "PTDATA - Parameter Table Data" },
158 { 0xd4, 4, "SBRS - SPI Bus Requester Status" },
159 { 0xe0, 4, "FREG12 - Flash Region" },
160 { 0xe4, 4, "FREG13 - Flash Region" },
161 { 0xe8, 4, "FREG14 - Flash Region" },
162 { 0xec, 4, "FREG15 - Flash Region" },
163 { 0x118, 4, "BM_WAP - BIOS Master Read Access Permissions (BIOS_BM_RAP)" },
164 { 0x11c, 4, "BM_WAP - BIOS Master Write Access Permissions (BIOS_BM_WAP)" },
165 { 0x184, 4, "CSXE_PR0 - CSXE Flash Protected Range" },
166 { 0x188, 4, "CSXE_PR1 - CSXE Flash Protected Range" },
167 { 0x18c, 4, "CSXE_PR2 - CSXE Flash Protected Range" },
168 { 0x190, 4, "CSXE_PR3 - CSXE Flash Protected Range" },
169 { 0x194, 4, "CSXE_PR4 - CSXE Flash Protected Range" },
170 { 0x198, 4, "CSXE_PR0 - CSXE Flash Protected Range" },
171 { 0x198, 4, "CSXE_WPR0 - Write Protected Range 0" },
172 };
173
174 static int print_bioscntl(struct pci_dev *sb)
175 {
176 int i, size = 0;
177 unsigned char bios_cntl = 0xff;
178 const io_register_t *bios_cntl_register = NULL;
179
180 printf("\n============= SPI / BIOS CNTL =============\n\n");
181
182 switch (sb->device_id) {
183 case PCI_DEVICE_ID_INTEL_ICH6:
184 bios_cntl = pci_read_byte(sb, 0xdc);
185 bios_cntl_register = ich6_bios_cntl_registers;
186 size = ARRAY_SIZE(ich6_bios_cntl_registers);
187 break;
188 case PCI_DEVICE_ID_INTEL_ICH7:
189 case PCI_DEVICE_ID_INTEL_ICH7M:
190 case PCI_DEVICE_ID_INTEL_ICH7DH:
191 case PCI_DEVICE_ID_INTEL_ICH7MDH:
192 case PCI_DEVICE_ID_INTEL_ICH8:
193 case PCI_DEVICE_ID_INTEL_ICH8M:
194 case PCI_DEVICE_ID_INTEL_ICH8ME:
195 case PCI_DEVICE_ID_INTEL_ICH9DH:
196 case PCI_DEVICE_ID_INTEL_ICH9DO:
197 case PCI_DEVICE_ID_INTEL_ICH9R:
198 case PCI_DEVICE_ID_INTEL_ICH9:
199 case PCI_DEVICE_ID_INTEL_ICH9M:
200 case PCI_DEVICE_ID_INTEL_ICH9ME:
201 case PCI_DEVICE_ID_INTEL_ICH10:
202 case PCI_DEVICE_ID_INTEL_ICH10D:
203 case PCI_DEVICE_ID_INTEL_ICH10DO:
204 case PCI_DEVICE_ID_INTEL_ICH10R:
205 case PCI_DEVICE_ID_INTEL_NM10:
206 bios_cntl = pci_read_byte(sb, 0xdc);
207 bios_cntl_register = ich7_bios_cntl_registers;
208 size = ARRAY_SIZE(ich7_bios_cntl_registers);
209 break;
210 case PCI_DEVICE_ID_INTEL_3400:
211 case PCI_DEVICE_ID_INTEL_3420:
212 case PCI_DEVICE_ID_INTEL_3450:
213 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
214 case PCI_DEVICE_ID_INTEL_B55_A:
215 case PCI_DEVICE_ID_INTEL_B55_B:
216 case PCI_DEVICE_ID_INTEL_H55:
217 case PCI_DEVICE_ID_INTEL_H57:
218 case PCI_DEVICE_ID_INTEL_P55:
219 case PCI_DEVICE_ID_INTEL_Q57:
220 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
221 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
222 case PCI_DEVICE_ID_INTEL_HM55:
223 case PCI_DEVICE_ID_INTEL_HM57:
224 case PCI_DEVICE_ID_INTEL_PM55:
225 case PCI_DEVICE_ID_INTEL_QM57:
226 case PCI_DEVICE_ID_INTEL_QS57:
227 case PCI_DEVICE_ID_INTEL_Z68:
228 case PCI_DEVICE_ID_INTEL_P67:
229 case PCI_DEVICE_ID_INTEL_UM67:
230 case PCI_DEVICE_ID_INTEL_HM65:
231 case PCI_DEVICE_ID_INTEL_H67:
232 case PCI_DEVICE_ID_INTEL_HM67:
233 case PCI_DEVICE_ID_INTEL_Q65:
234 case PCI_DEVICE_ID_INTEL_QS67:
235 case PCI_DEVICE_ID_INTEL_Q67:
236 case PCI_DEVICE_ID_INTEL_QM67:
237 case PCI_DEVICE_ID_INTEL_B65:
238 case PCI_DEVICE_ID_INTEL_C202:
239 case PCI_DEVICE_ID_INTEL_C204:
240 case PCI_DEVICE_ID_INTEL_C206:
241 case PCI_DEVICE_ID_INTEL_H61:
242 case PCI_DEVICE_ID_INTEL_Z77:
243 case PCI_DEVICE_ID_INTEL_Z75:
244 case PCI_DEVICE_ID_INTEL_Q77:
245 case PCI_DEVICE_ID_INTEL_Q75:
246 case PCI_DEVICE_ID_INTEL_B75:
247 case PCI_DEVICE_ID_INTEL_H77:
248 case PCI_DEVICE_ID_INTEL_C216:
249 case PCI_DEVICE_ID_INTEL_QM77:
250 case PCI_DEVICE_ID_INTEL_QS77:
251 case PCI_DEVICE_ID_INTEL_HM77:
252 case PCI_DEVICE_ID_INTEL_UM77:
253 case PCI_DEVICE_ID_INTEL_HM76:
254 case PCI_DEVICE_ID_INTEL_HM75:
255 case PCI_DEVICE_ID_INTEL_HM70:
256 case PCI_DEVICE_ID_INTEL_NM70:
257 case PCI_DEVICE_ID_INTEL_C8_MOBILE:
258 case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
259 case PCI_DEVICE_ID_INTEL_Z87:
260 case PCI_DEVICE_ID_INTEL_Z85:
261 case PCI_DEVICE_ID_INTEL_HM86:
262 case PCI_DEVICE_ID_INTEL_H87:
263 case PCI_DEVICE_ID_INTEL_HM87:
264 case PCI_DEVICE_ID_INTEL_Q85:
265 case PCI_DEVICE_ID_INTEL_Q87:
266 case PCI_DEVICE_ID_INTEL_QM87:
267 case PCI_DEVICE_ID_INTEL_B85:
268 case PCI_DEVICE_ID_INTEL_C222:
269 case PCI_DEVICE_ID_INTEL_C224:
270 case PCI_DEVICE_ID_INTEL_C226:
271 case PCI_DEVICE_ID_INTEL_H81:
272 case PCI_DEVICE_ID_INTEL_C9_MOBILE:
273 case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
274 case PCI_DEVICE_ID_INTEL_HM97:
275 case PCI_DEVICE_ID_INTEL_Z97:
276 case PCI_DEVICE_ID_INTEL_H97:
277 case PCI_DEVICE_ID_INTEL_H110:
278 case PCI_DEVICE_ID_INTEL_H170:
279 case PCI_DEVICE_ID_INTEL_Z170:
280 case PCI_DEVICE_ID_INTEL_Q170:
281 case PCI_DEVICE_ID_INTEL_Q150:
282 case PCI_DEVICE_ID_INTEL_B150:
283 case PCI_DEVICE_ID_INTEL_C236:
284 case PCI_DEVICE_ID_INTEL_C232:
285 case PCI_DEVICE_ID_INTEL_QM170:
286 case PCI_DEVICE_ID_INTEL_HM170:
287 case PCI_DEVICE_ID_INTEL_CM236:
288 case PCI_DEVICE_ID_INTEL_HM175:
289 case PCI_DEVICE_ID_INTEL_QM175:
290 case PCI_DEVICE_ID_INTEL_CM238:
291 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
292 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
293 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
294 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
295 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
296 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
297 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
298 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
299 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
300 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
301 bios_cntl = pci_read_byte(sb, 0xdc);
302 bios_cntl_register = pch_bios_cntl_registers;
303 size = ARRAY_SIZE(pch_bios_cntl_registers);
304 break;
305 case PCI_DEVICE_ID_INTEL_ADL_N:
306 bios_cntl = pci_read_byte(sb, 0xdc);
307 bios_cntl_register = adl_pch_bios_cntl_registers;
308 size = ARRAY_SIZE(adl_pch_bios_cntl_registers);
309 break;
310 case PCI_DEVICE_ID_INTEL_EHL:
311 bios_cntl = pci_read_byte(sb, 0xdc);
312 bios_cntl_register = elkhart_bios_cntl_registers;
313 size = ARRAY_SIZE(elkhart_bios_cntl_registers);
314 break;
315 default:
316 printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
317 return 1;
318 }
319
320 printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl);
321
322 if (bios_cntl_register) {
323 for (i = 0; i < size; i++) {
324 unsigned int val = bios_cntl >> bios_cntl_register[i].addr;
325 val &= ((1 << bios_cntl_register[i].size) -1);
326 printf("0x%04x = %s\n", val, bios_cntl_register[i].name);
327 }
328 }
329
330 return 0;
331 }
332
333 static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) {
334 int i, size = 0, rcba_size = 0x4000;
335 volatile uint8_t *rcba;
336 uint32_t rcba_phys;
337 const io_register_t *spi_register = NULL;
338 uint32_t spibaroffset;
339 struct pci_dev *spidev;
340
341 printf("\n============= SPI Bar ==============\n\n");
342
343 switch (sb->device_id) {
344 case PCI_DEVICE_ID_INTEL_ICH6:
345 printf("This southbridge does not have a SPI controller.\n");
346 return 1;
347 case PCI_DEVICE_ID_INTEL_ICH7:
348 case PCI_DEVICE_ID_INTEL_ICH7M:
349 case PCI_DEVICE_ID_INTEL_ICH7DH:
350 case PCI_DEVICE_ID_INTEL_ICH7MDH:
351 spibaroffset = ICH78_SPIBAR;
352 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
353 size = ARRAY_SIZE(ich7_spi_bar_registers);
354 spi_register = ich7_spi_bar_registers;
355 break;
356 case PCI_DEVICE_ID_INTEL_ICH8:
357 spibaroffset = ICH78_SPIBAR;
358 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
359 size = ARRAY_SIZE(spi_bar_registers);
360 spi_register = spi_bar_registers;
361 break;
362 case PCI_DEVICE_ID_INTEL_ICH8M:
363 case PCI_DEVICE_ID_INTEL_ICH8ME:
364 case PCI_DEVICE_ID_INTEL_ICH9DH:
365 case PCI_DEVICE_ID_INTEL_ICH9DO:
366 case PCI_DEVICE_ID_INTEL_ICH9R:
367 case PCI_DEVICE_ID_INTEL_ICH9:
368 case PCI_DEVICE_ID_INTEL_ICH9M:
369 case PCI_DEVICE_ID_INTEL_ICH9ME:
370 case PCI_DEVICE_ID_INTEL_ICH10:
371 case PCI_DEVICE_ID_INTEL_ICH10D:
372 case PCI_DEVICE_ID_INTEL_ICH10DO:
373 case PCI_DEVICE_ID_INTEL_ICH10R:
374 case PCI_DEVICE_ID_INTEL_NM10:
375 case PCI_DEVICE_ID_INTEL_I63XX:
376 case PCI_DEVICE_ID_INTEL_3400:
377 case PCI_DEVICE_ID_INTEL_3420:
378 case PCI_DEVICE_ID_INTEL_3450:
379 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
380 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
381 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
382 case PCI_DEVICE_ID_INTEL_B55_A:
383 case PCI_DEVICE_ID_INTEL_B55_B:
384 case PCI_DEVICE_ID_INTEL_H55:
385 case PCI_DEVICE_ID_INTEL_H57:
386 case PCI_DEVICE_ID_INTEL_HM55:
387 case PCI_DEVICE_ID_INTEL_HM57:
388 case PCI_DEVICE_ID_INTEL_P55:
389 case PCI_DEVICE_ID_INTEL_PM55:
390 case PCI_DEVICE_ID_INTEL_Q57:
391 case PCI_DEVICE_ID_INTEL_QM57:
392 case PCI_DEVICE_ID_INTEL_QS57:
393 case PCI_DEVICE_ID_INTEL_Z68:
394 case PCI_DEVICE_ID_INTEL_P67:
395 case PCI_DEVICE_ID_INTEL_UM67:
396 case PCI_DEVICE_ID_INTEL_HM65:
397 case PCI_DEVICE_ID_INTEL_H67:
398 case PCI_DEVICE_ID_INTEL_HM67:
399 case PCI_DEVICE_ID_INTEL_Q65:
400 case PCI_DEVICE_ID_INTEL_QS67:
401 case PCI_DEVICE_ID_INTEL_Q67:
402 case PCI_DEVICE_ID_INTEL_QM67:
403 case PCI_DEVICE_ID_INTEL_B65:
404 case PCI_DEVICE_ID_INTEL_C202:
405 case PCI_DEVICE_ID_INTEL_C204:
406 case PCI_DEVICE_ID_INTEL_C206:
407 case PCI_DEVICE_ID_INTEL_H61:
408 case PCI_DEVICE_ID_INTEL_Z77:
409 case PCI_DEVICE_ID_INTEL_Z75:
410 case PCI_DEVICE_ID_INTEL_Q77:
411 case PCI_DEVICE_ID_INTEL_Q75:
412 case PCI_DEVICE_ID_INTEL_B75:
413 case PCI_DEVICE_ID_INTEL_H77:
414 case PCI_DEVICE_ID_INTEL_C216:
415 case PCI_DEVICE_ID_INTEL_QM77:
416 case PCI_DEVICE_ID_INTEL_QS77:
417 case PCI_DEVICE_ID_INTEL_HM77:
418 case PCI_DEVICE_ID_INTEL_UM77:
419 case PCI_DEVICE_ID_INTEL_HM76:
420 case PCI_DEVICE_ID_INTEL_HM75:
421 case PCI_DEVICE_ID_INTEL_HM70:
422 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
423 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
424 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
425 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
426 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
427 case PCI_DEVICE_ID_INTEL_C8_MOBILE:
428 case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
429 case PCI_DEVICE_ID_INTEL_Z87:
430 case PCI_DEVICE_ID_INTEL_Z85:
431 case PCI_DEVICE_ID_INTEL_HM86:
432 case PCI_DEVICE_ID_INTEL_H87:
433 case PCI_DEVICE_ID_INTEL_HM87:
434 case PCI_DEVICE_ID_INTEL_Q85:
435 case PCI_DEVICE_ID_INTEL_Q87:
436 case PCI_DEVICE_ID_INTEL_QM87:
437 case PCI_DEVICE_ID_INTEL_B85:
438 case PCI_DEVICE_ID_INTEL_C222:
439 case PCI_DEVICE_ID_INTEL_C224:
440 case PCI_DEVICE_ID_INTEL_C226:
441 case PCI_DEVICE_ID_INTEL_H81:
442 case PCI_DEVICE_ID_INTEL_C9_MOBILE:
443 case PCI_DEVICE_ID_INTEL_C9_DESKTOP:
444 case PCI_DEVICE_ID_INTEL_HM97:
445 case PCI_DEVICE_ID_INTEL_Z97:
446 case PCI_DEVICE_ID_INTEL_H97:
447 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
448 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
449 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
450 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
451 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
452 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
453 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
454 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
455 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
456 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
457 spibaroffset = ICH9_SPIBAR;
458 rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
459 size = ARRAY_SIZE(spi_bar_registers);
460 spi_register = spi_bar_registers;
461 break;
462 case PCI_DEVICE_ID_INTEL_EHL:
463 /* the southbridge is the eSPI controller, we need to get the SPI flash controller */
464 if (!(spidev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 5))) {
465 perror("Error: no spi device 0:31.5\n");
466 return 1;
467 }
468
469 rcba_phys = ((uint64_t)pci_read_long(spidev, 0x10) & 0xfffff000);
470 rcba_size = 4096;
471 if (!rcba_phys) {
472 fprintf(stderr, "Error: no valid bar 0 of device 0:31.5 found %x %x\n", rcba_phys, rcba_size);
473 return 1;
474 }
475
476 /* this is not rcba, but we keep it to use common code */
477 spibaroffset = 0;
478 spi_register = elkhart_spi_bar_registers;
479 size = ARRAY_SIZE(elkhart_spi_bar_registers);
480 break;
481 case PCI_DEVICE_ID_INTEL_ICH:
482 case PCI_DEVICE_ID_INTEL_ICH0:
483 case PCI_DEVICE_ID_INTEL_ICH2:
484 case PCI_DEVICE_ID_INTEL_ICH4:
485 case PCI_DEVICE_ID_INTEL_ICH4M:
486 case PCI_DEVICE_ID_INTEL_ICH5:
487 case PCI_DEVICE_ID_INTEL_ADL_N:
488 printf("This southbridge does not have RCBA.\n");
489 return 1;
490 default:
491 printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
492 return 1;
493 }
494
495 rcba = map_physical(rcba_phys, rcba_size);
496 if (rcba == NULL) {
497 perror("Error mapping RCBA");
498 exit(1);
499 }
500
501 for (i = 0; i < size; i++) {
502 switch(spi_register[i].size) {
503 case 1:
504 printf("0x%08x = %s\n", read8(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
505 break;
506 case 2:
507 printf("0x%08x = %s\n", read16(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
508 break;
509 case 4:
510 printf("0x%08x = %s\n", read32(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
511 break;
512 case 8:
513 printf("0x%08x%08x = %s\n", read32(rcba + spibaroffset + spi_register[i].addr + 4),
514 read32(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
515 break;
516 }
517 }
518
519 unmap_physical((void *)rcba, rcba_size);
520 return 0;
521 }
522
523 int print_spi(struct pci_dev *sb, struct pci_access *pacc) {
524 return (print_bioscntl(sb) || print_spibar(sb, pacc));
525 }
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