payloads/libpayload/drivers/serial/ipq806x.c

   1 /*
   2  * Copyright (c) 2014 ChromiumOS authors
   3  */
   4
   5 #include <libpayload.h>
   6
   7 enum IPQ_UART_DM_PARITY_MODE {
   8         IPQ_UART_DM_NO_PARITY,
   9         IPQ_UART_DM_ODD_PARITY,
  10         IPQ_UART_DM_EVEN_PARITY,
  11         IPQ_UART_DM_SPACE_PARITY
  12 };
  13
  14 /* UART Stop Bit Length */
  15 enum IPQ_UART_DM_STOP_BIT_LEN {
  16         IPQ_UART_DM_SBL_9_16,
  17         IPQ_UART_DM_SBL_1,
  18         IPQ_UART_DM_SBL_1_9_16,
  19         IPQ_UART_DM_SBL_2
  20 };
  21
  22 /* UART Bits per Char */
  23 enum IPQ_UART_DM_BITS_PER_CHAR {
  24         IPQ_UART_DM_5_BPS,
  25         IPQ_UART_DM_6_BPS,
  26         IPQ_UART_DM_7_BPS,
  27         IPQ_UART_DM_8_BPS
  28 };
  29
  30 #define IPQ_UART_DM_CR(base)            (((u8 *)(base)) + 0x10)
  31 #define IPQ_UART_DM_DMEN(base)          (((u8 *)(base)) + 0x3C)
  32 #define IPQ_UART_DM_DMRX(base)          (((u8 *)(base)) + 0x34)
  33 #define IPQ_UART_DM_HCR(base)           (((u8 *)(base)) + 0x24)
  34 #define IPQ_UART_DM_IMR(base)           (((u8 *)(base)) + 0x14)
  35 #define IPQ_UART_DM_IPR(base)           (((u8 *)(base)) + 0x18)
  36 #define IPQ_UART_DM_IRDA(base)          (((u8 *)(base)) + 0x38)
  37 #define IPQ_UART_DM_MISR(base)          (((u8 *)(base)) + 0x10)
  38 #define IPQ_UART_DM_MR1(base)           (((u8 *)(base)) + 0x00)
  39 #define IPQ_UART_DM_MR2(base)           (((u8 *)(base)) + 0x04)
  40 #define IPQ_UART_DM_NO_CHARS_FOR_TX(base) (((u8 *)(base)) + 0x040)
  41 #define IPQ_UART_DM_RF(base, x)         (((u8 *)(base)) + 0x70 + 4*(x))
  42 #define IPQ_UART_DM_RFWR(base)          (((u8 *)(base)) + 0x20)
  43 #define IPQ_UART_DM_RX_TOTAL_SNAP(base) (((u8 *)(base)) + 0x38)
  44 #define IPQ_UART_DM_SR(base)            (((u8 *)(base)) + 0x008)
  45 #define IPQ_UART_DM_TF(base, x)         (((u8 *)(base)) + 0x70 + 4*(x))
  46 #define IPQ_UART_DM_TFWR(base)          (((u8 *)(base)) + 0x1C)
  47
  48 #define IPQ_UART_DM_TXLEV               (1 << 0)
  49 #define IPQ_UART_DM_TX_READY            (1 << 7)
  50
  51 #define IPQ_UART_DM_CR_CH_CMD_LSB(x)    ((x & 0x0f) << 4)
  52 #define IPQ_UART_DM_CR_CH_CMD_MSB(x)    ((x >> 4 ) << 11 )
  53 #define IPQ_UART_DM_CR_CH_CMD(x)        (IPQ_UART_DM_CR_CH_CMD_LSB(x)\
  54                                              | IPQ_UART_DM_CR_CH_CMD_MSB(x))
  55
  56 #define IPQ_UART_DM_CR_GENERAL_CMD(x)   ((x) << 8)
  57
  58 #define IPQ_UART_DM_8_N_1_MODE          (IPQ_UART_DM_NO_PARITY | \
  59                                              (IPQ_UART_DM_SBL_1 << 2) | \
  60                                              (IPQ_UART_DM_8_BPS << 4))
  61 #define IPQ_UART_DM_CR_RX_ENABLE        (1 << 0)
  62 #define IPQ_UART_DM_CR_TX_ENABLE        (1 << 2)
  63 #define IPQ_UART_DM_CMD_RESET_RX        IPQ_UART_DM_CR_CH_CMD(1)
  64 #define IPQ_UART_DM_CMD_RESET_TX        IPQ_UART_DM_CR_CH_CMD(2)
  65 #define IPQ_UART_DM_CMD_RESET_ERR_STAT  IPQ_UART_DM_CR_CH_CMD(3)
  66 #define IPQ_UART_DM_CMD_RES_STALE_INT   IPQ_UART_DM_CR_CH_CMD(8)
  67 #define IPQ_UART_DM_CMD_RES_TX_ERR      IPQ_UART_DM_CR_CH_CMD(10)
  68 #define IPQ_UART_DM_GCMD_ENA_STALE_EVT   IPQ_UART_DM_CR_GENERAL_CMD(5)
  69 #define IPQ_UART_DM_RXSTALE             (1 << 3)
  70 #define IPQ_UART_DM_IMR_ENABLED         (IPQ_UART_DM_TX_READY | \
  71                                               IPQ_UART_DM_TXLEV    | \
  72                                               IPQ_UART_DM_RXSTALE)
  73 #define IPQ_UART_DM_TFW_VALUE           0
  74 #define IPQ_UART_DM_RFW_VALUE           1
  75 #define IPQ_UART_DM_DMRX_DEF_VALUE      0x220
  76 #define IPQ_UART_DM_SR_TXEMT            (1 << 3)
  77 #define IPQ_UART_DM_SR_UART_OVERRUN     (1 << 4)
  78 #define IPQ_UART_DM_E_SUCCESS           0
  79 #define IPQ_UART_DM_E_INVAL             3
  80 #define IPQ_UART_DM_E_RX_NOT_READY      5
  81
  82 #define IPQ_UART_DM_STALE_TIMEOUT_LSB   0x0f
  83
  84 static struct console_input_driver consin = {};
  85 static struct console_output_driver consout = {};
  86
  87 #define FIFO_DATA_SIZE  4
  88
  89 static void  *base_uart_addr;
  90
  91 /*
  92  * All constants lifted from u-boot's
  93  * board/qcom/ipq806x_cdp/ipq806x_board_param.h
  94  */
  95 static unsigned int msm_boot_uart_dm_init(void *uart_dm_base);
  96
  97 /* Number of pending received characters */
  98 static int uart_ready_data_count;
  99
 100 /* Received data as it came from 32 bit wide FIFO */
 101 static unsigned int uart_rx_fifo_word;
 102
 103 /**
 104  * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
 105  * @uart_dm_base: UART controller base address
 106  */
 107 static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
 108 {
 109         /* Reset receiver */
 110         writel(IPQ_UART_DM_CMD_RESET_RX,
 111                 IPQ_UART_DM_CR(uart_dm_base));
 112
 113         /* Enable receiver */
 114         writel(IPQ_UART_DM_CR_RX_ENABLE,
 115                 IPQ_UART_DM_CR(uart_dm_base));
 116         writel(IPQ_UART_DM_DMRX_DEF_VALUE,
 117                 IPQ_UART_DM_DMRX(uart_dm_base));
 118
 119         /* Clear stale event */
 120         writel(IPQ_UART_DM_CMD_RES_STALE_INT,
 121                 IPQ_UART_DM_CR(uart_dm_base));
 122
 123         /* Enable stale event */
 124         writel(IPQ_UART_DM_GCMD_ENA_STALE_EVT,
 125                 IPQ_UART_DM_CR(uart_dm_base));
 126
 127         return IPQ_UART_DM_E_SUCCESS;
 128 }
 129
 130 /**
 131  * Reads a word from the RX FIFO or returns not ready.
 132  */
 133 static unsigned msm_boot_uart_dm_read(void)
 134 {
 135         static int total_rx_data = 0;
 136         static int rx_data_read = 0;
 137         void  *base = base_uart_addr;
 138         uint32_t status_reg;
 139
 140         /* RXSTALE means RX FIFO is not empty. */
 141         status_reg = readl(IPQ_UART_DM_MISR(base));
 142         if (!(status_reg & IPQ_UART_DM_RXSTALE))
 143                 return IPQ_UART_DM_E_RX_NOT_READY;
 144
 145         /* Check for Overrun error. We'll just reset Error Status */
 146         if (readl(IPQ_UART_DM_SR(base)) &
 147                         IPQ_UART_DM_SR_UART_OVERRUN) {
 148                 writel(IPQ_UART_DM_CMD_RESET_ERR_STAT,
 149                         IPQ_UART_DM_CR(base));
 150                 total_rx_data = rx_data_read = 0;
 151                 msm_boot_uart_dm_init(base);
 152                 return IPQ_UART_DM_E_RX_NOT_READY;
 153         }
 154
 155         /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
 156         if (total_rx_data == 0)
 157                 total_rx_data =  readl(IPQ_UART_DM_RX_TOTAL_SNAP(base));
 158
 159         /* Data available in FIFO; read a word. */
 160         uart_rx_fifo_word = readl(IPQ_UART_DM_RF(base, 0));
 161
 162         /*
 163          * TODO(vbendeb): this is wrong and will be addressed shortly: there
 164          * should be no zeros returned from the FIFO in case there are
 165          * received characters (we don't expect to be receiving zeros).
 166          * See http://crosbug.com/p/29313
 167          */
 168         if (uart_rx_fifo_word == 0) {
 169                 return IPQ_UART_DM_E_RX_NOT_READY;
 170         }
 171
 172         /* increment the total count of chars we've read so far */
 173         rx_data_read += FIFO_DATA_SIZE;
 174
 175         /* Actual count of valid data in word */
 176         uart_ready_data_count =
 177                 ((total_rx_data < rx_data_read) ?
 178                  (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
 179                  FIFO_DATA_SIZE);
 180
 181         /* If there are still data left in FIFO we'll read them before
 182          * initializing RX Transfer again
 183          */
 184         if (rx_data_read < total_rx_data)
 185                 return IPQ_UART_DM_E_SUCCESS;
 186
 187         msm_boot_uart_dm_init_rx_transfer(base);
 188         total_rx_data = rx_data_read = 0;
 189
 190         return IPQ_UART_DM_E_SUCCESS;
 191 }
 192
 193 void serial_putchar(unsigned data)
 194 {
 195         int num_of_chars = 0;
 196         unsigned tx_data = 0;
 197         void *base = base_uart_addr;
 198
 199         if (data == '\n') {
 200                 num_of_chars++;
 201                 tx_data = '\r';
 202         }
 203
 204         tx_data  |= data << (8 * num_of_chars++);
 205
 206         /* Wait until transmit FIFO is empty. */
 207         while (!(readl(IPQ_UART_DM_SR(base)) &
 208                  IPQ_UART_DM_SR_TXEMT))
 209                 udelay(1);
 210
 211         /*
 212          * TX FIFO is ready to accept new character(s). First write number of
 213          * characters to be transmitted.
 214          */
 215         writel(num_of_chars, IPQ_UART_DM_NO_CHARS_FOR_TX(base));
 216
 217         /* And now write the character(s) */
 218         writel(tx_data, IPQ_UART_DM_TF(base, 0));
 219 }
 220
 221 /*
 222  * msm_boot_uart_dm_reset - resets UART controller
 223  * @base: UART controller base address
 224  */
 225 static unsigned int msm_boot_uart_dm_reset(void *base)
 226 {
 227         writel(IPQ_UART_DM_CMD_RESET_RX, IPQ_UART_DM_CR(base));
 228         writel(IPQ_UART_DM_CMD_RESET_TX, IPQ_UART_DM_CR(base));
 229         writel(IPQ_UART_DM_CMD_RESET_ERR_STAT,
 230                  IPQ_UART_DM_CR(base));
 231         writel(IPQ_UART_DM_CMD_RES_TX_ERR, IPQ_UART_DM_CR(base));
 232         writel(IPQ_UART_DM_CMD_RES_STALE_INT, IPQ_UART_DM_CR(base));
 233
 234         return IPQ_UART_DM_E_SUCCESS;
 235 }
 236
 237 /*
 238  * msm_boot_uart_dm_init - Initializes UART controller
 239  * @uart_dm_base: UART controller base address
 240  */
 241 static unsigned int msm_boot_uart_dm_init(void  *uart_dm_base)
 242 {
 243         /* Configure UART mode registers MR1 and MR2 */
 244         /* Hardware flow control isn't supported */
 245         writel(0x0, IPQ_UART_DM_MR1(uart_dm_base));
 246
 247         /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
 248         writel(IPQ_UART_DM_8_N_1_MODE,
 249                  IPQ_UART_DM_MR2(uart_dm_base));
 250
 251         /* Configure Interrupt Mask register IMR */
 252         writel(IPQ_UART_DM_IMR_ENABLED,
 253                  IPQ_UART_DM_IMR(uart_dm_base));
 254
 255         /*
 256          * Configure Tx and Rx watermarks configuration registers
 257          * TX watermark value is set to 0 - interrupt is generated when
 258          * FIFO level is less than or equal to 0
 259          */
 260         writel(IPQ_UART_DM_TFW_VALUE,
 261                  IPQ_UART_DM_TFWR(uart_dm_base));
 262
 263         /* RX watermark value */
 264         writel(IPQ_UART_DM_RFW_VALUE,
 265                  IPQ_UART_DM_RFWR(uart_dm_base));
 266
 267         /* Configure Interrupt Programming Register */
 268         /* Set initial Stale timeout value */
 269         writel(IPQ_UART_DM_STALE_TIMEOUT_LSB,
 270                 IPQ_UART_DM_IPR(uart_dm_base));
 271
 272         /* Configure IRDA if required */
 273         /* Disabling IRDA mode */
 274         writel(0x0, IPQ_UART_DM_IRDA(uart_dm_base));
 275
 276         /* Configure hunt character value in HCR register */
 277         /* Keep it in reset state */
 278         writel(0x0, IPQ_UART_DM_HCR(uart_dm_base));
 279
 280         /*
 281          * Configure Rx FIFO base address
 282          * Both TX/RX shares same SRAM and default is half-n-half.
 283          * Sticking with default value now.
 284          * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
 285          * We have found RAM_ADDR_WIDTH = 0x7f
 286          */
 287
 288         /* Issue soft reset command */
 289         msm_boot_uart_dm_reset(uart_dm_base);
 290
 291         /* Enable/Disable Rx/Tx DM interfaces */
 292         /* Data Mover not currently utilized. */
 293         writel(0, IPQ_UART_DM_DMEN(uart_dm_base));
 294
 295         /* Enable transmitter */
 296         writel(IPQ_UART_DM_CR_TX_ENABLE,
 297                 IPQ_UART_DM_CR(uart_dm_base));
 298
 299         /* Initialize Receive Path */
 300         msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
 301
 302         return 0;
 303 }
 304
 305 /**
 306  * serial_havechar - checks if data available for reading
 307  *
 308  * Returns 1 if data available, 0 otherwise
 309  */
 310 int serial_havechar(void)
 311 {
 312         /* Return if data is already read */
 313         if (uart_ready_data_count)
 314                 return 1;
 315
 316         /* Read data from the FIFO */
 317         if (msm_boot_uart_dm_read() != IPQ_UART_DM_E_SUCCESS)
 318                 return 0;
 319
 320         return 1;
 321 }
 322
 323 /**
 324  * ipq806x_serial_getc - reads a character
 325  *
 326  * Returns the character read from serial port.
 327  */
 328 int serial_getchar(void)
 329 {
 330         uint8_t byte;
 331
 332         while (!serial_havechar()) {
 333                 /* wait for incoming data */
 334         }
 335
 336         byte = (uint8_t)(uart_rx_fifo_word & 0xff);
 337         uart_rx_fifo_word = uart_rx_fifo_word >> 8;
 338         uart_ready_data_count--;
 339
 340         return byte;
 341 }
 342
 343 /* For simplicity's sake, let's rely on coreboot initializing the UART. */
 344 void serial_console_init(void)
 345 {
 346         struct cb_serial *sc_ptr = phys_to_virt(lib_sysinfo.cb_serial);
 347
 348         if (!lib_sysinfo.cb_serial)
 349                 return;
 350
 351         base_uart_addr = (void *) sc_ptr->baseaddr;
 352
 353         consin.havekey = serial_havechar;
 354         consin.getchar = serial_getchar;
 355         consin.input_type = CONSOLE_INPUT_TYPE_UART;
 356
 357         consout.putchar = serial_putchar;
 358
 359         console_add_output_driver(&consout);
 360         console_add_input_driver(&consin);
 361 }