payloads/libpayload/drivers/udc/chipidea_priv.h

   1 /*
   2  *
   3  * Copyright (C) 2015 Google Inc.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. The name of the author may not be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CHIPIDEA_PRIV_H__
  30 #define __CHIPIDEA_PRIV_H__
  31
  32 #include <queue.h>
  33
  34 struct chipidea_opreg {
  35         uint8_t pad0[0x130];
  36         uint32_t usbcmd; // 0x130
  37         uint32_t usbsts; // 0x134
  38         uint32_t pad138[3];
  39         uint32_t usbadr; // 0x144
  40                 /* 31:25: address
  41                  * 24: staging: 1 -> commit new address after
  42                  *                   next ctrl-in on ep0
  43                  */
  44         uint32_t epbase; // 0x148
  45         uint32_t pad14c[10];
  46         uint32_t portsc; // 0x174
  47         uint32_t pad178[15];
  48         uint32_t devlc; // 0x1b4
  49                 /* 25:26: host-desired USB version
  50                  * 23: force full speed */
  51         uint32_t pad1b8[16];
  52         uint32_t usbmode; // 0x1f8
  53                 /* 0:1: 2 -> device mode */
  54         uint32_t pad1fc[3];
  55         uint32_t epsetupstat; // 0x208
  56                 /* 0:15: 1 -> epX received setup packet */
  57         uint32_t epprime; // 0x20c
  58                 /*  0:15: 1 -> rx buffer for epX (OUT) is primed
  59                  *             (ie. ready for controller-side processing)
  60                  * 16:31: 1 -> tx buffer for ep(X-16) (IN/INTR) is primed
  61                  *             (ie. ready for controller-side processing)
  62                  *
  63                  * controller will read new td from qh and process it,
  64                  * then set the bit to 0
  65                  */
  66         uint32_t epflush; // 0x210
  67                 /* 0:31: 1 -> flush buffer (as defined in epprime),
  68                  *            so it's uninitialized again.
  69                  * controller resets to 0 when done
  70                  */
  71         uint32_t epstat; // 0x214
  72                 /* 0:31: 1 -> command in epprime is done, EP is ready
  73                  *           (which may be later than epprime reset)
  74                  */
  75         uint32_t epcomplete; // 0x218
  76                 /*  0:15: 1 -> incoming out/setup packet for epX was handled.
  77                  *             software should check QH state
  78                  * 16:31: 1 -> incoming intr/in packet for ep(X-16) was
  79                  *             handled. software should check QH state
  80                  */
  81         uint32_t epctrl[16]; // 0x21c
  82                 /* epctrl[0] is hardcoded as enabled control endpoint.
  83                  * TXS/RXS for stalling can be written.
  84                  *
  85                  * 23: TXE tx endpoint enable
  86                  * 22: TXR reset tx data toggle (for every configuration event)
  87                  * 18:19: 0=ctrl, 1=isoc, 2=bulk, 3=intr endpoint
  88                  * 16: TXS stall tx
  89                  *
  90                  *  7: RXE rx endpoint enable
  91                  *  6: RXR reset rx data toggle (for every configuration event)
  92                  *  2:3: endpoint type (like 18:19)
  93                  *  0: RXS stall rx
  94                  */
  95         uint32_t pad25c[0x69]; // 0x25c
  96         uint32_t susp_ctrl; // 0x400
  97 };
  98
  99 #define CI_PDATA(ctrl) ((struct chipidea_pdata *)((ctrl)->pdata))
 100 #define CI_QHELEMENTS 32
 101
 102 #define QH_NO_AUTO_ZLT (1 << 29) /* no automatic ZLT handling by chipset */
 103 #define QH_MPS(x) ((x) << 16)
 104 #define QH_IOS (1 << 15) /* IRQ on setup */
 105
 106 #define TD_INFO_LEN(x) ((x) << 16)
 107 #define TD_INFO_IOC (1 << 15)
 108 #define TD_INFO_ACTIVE (1 << 7)
 109 #define TD_TERMINATE 1
 110
 111 #define USBCMD_8MICRO (8 << 16)
 112 #define USBCMD_RST 2
 113 #define USBCMD_RUN 1
 114
 115 #define USBSTS_SLI (1 << 8)
 116 #define USBSTS_URI (1 << 6)
 117 #define USBSTS_PCI (1 << 2)
 118 #define USBSTS_UEI (1 << 1)
 119 #define USBSTS_UI  (1 << 0)
 120
 121 #define DEVLC_HOSTSPEED(x) (x << 25)
 122 #define DEVLC_HOSTSPEED_MASK DEVLC_HOSTSPEED(3)
 123
 124 struct td {
 125         /* points to next td */
 126         uint32_t next;
 127         uint32_t info;
 128         /* page0..4 are like EHCI pages: up to 4k each
 129          * page0 from addr to page end, page4 to its length
 130          */
 131         uint32_t page0;
 132         uint32_t page1;
 133         uint32_t page2;
 134         uint32_t page3;
 135         uint32_t page4;
 136         uint32_t res;
 137 };
 138
 139 struct qh {
 140         uint32_t config;
 141         uint32_t current;
 142         struct td td;
 143         /* contains the data of a setup request */
 144         uint8_t setup_data[8];
 145         uint32_t res[4];
 146 };
 147
 148 struct job {
 149         SIMPLEQ_ENTRY(job) queue; // linkage
 150         struct td *tds; // for later free()ing
 151         int td_count;
 152         void *data;
 153         size_t length;
 154         int zlp; // append zero length packet?
 155         int autofree; // free after processing?
 156 };
 157
 158 SIMPLEQ_HEAD(job_queue, job);
 159
 160 struct chipidea_pdata {
 161         struct chipidea_opreg *opreg;
 162         struct qh *qhlist;
 163         struct job_queue job_queue[16][2];
 164         int ep_busy[16][2];
 165 };
 166
 167 #endif