src/commonlib/storage/sdhci.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Secure Digital (SD) Host Controller interface specific code
   4  */
   5
   6 #include "bouncebuf.h"
   7 #include <commonlib/sd_mmc_ctrlr.h>
   8 #include <commonlib/sdhci.h>
   9 #include <commonlib/bsd/stdlib.h>
  10 #include <commonlib/storage.h>
  11 #include <delay.h>
  12 #include <endian.h>
  13 #include <lib.h>
  14 #include "sdhci.h"
  15 #include "sd_mmc.h"
  16 #include "storage.h"
  17 #include <timer.h>
  18
  19 #define DMA_AVAILABLE   ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \
  20                         || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_SEPARATE_VERSTAGE) \
  21                         || (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_SEPARATE_ROMSTAGE) \
  22                         || ENV_POSTCAR || ENV_RAMSTAGE)
  23
  24 void sdhci_reset(struct sdhci_ctrlr *sdhci_ctrlr, u8 mask)
  25 {
  26         struct stopwatch sw;
  27
  28         /* Wait max 100 ms */
  29         stopwatch_init_msecs_expire(&sw, 100);
  30
  31         sdhci_writeb(sdhci_ctrlr, mask, SDHCI_SOFTWARE_RESET);
  32         while (sdhci_readb(sdhci_ctrlr, SDHCI_SOFTWARE_RESET) & mask) {
  33                 if (stopwatch_expired(&sw)) {
  34                         sdhc_error("Reset 0x%x never completed.\n", (int)mask);
  35                         return;
  36                 }
  37                 udelay(1000);
  38         }
  39 }
  40
  41 void sdhci_cmd_done(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_command *cmd)
  42 {
  43         int i;
  44         if (cmd->resp_type & CARD_RSP_136) {
  45                 /* CRC is stripped so we need to do some shifting. */
  46                 for (i = 0; i < 4; i++) {
  47                         cmd->response[i] = sdhci_readl(sdhci_ctrlr,
  48                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  49                         if (i != 3)
  50                                 cmd->response[i] |= sdhci_readb(sdhci_ctrlr,
  51                                                 SDHCI_RESPONSE + (3-i)*4-1);
  52                 }
  53                 sdhc_log_response(4, &cmd->response[0]);
  54                 sdhc_trace("Response: 0x%08x.%08x.%08x.%08x\n",
  55                         cmd->response[3], cmd->response[2], cmd->response[1],
  56                         cmd->response[0]);
  57         } else {
  58                 cmd->response[0] = sdhci_readl(sdhci_ctrlr, SDHCI_RESPONSE);
  59                 sdhc_log_response(1, &cmd->response[0]);
  60                 sdhc_trace("Response: 0x%08x\n", cmd->response[0]);
  61         }
  62 }
  63
  64 static int sdhci_transfer_data(struct sdhci_ctrlr *sdhci_ctrlr,
  65         struct mmc_data *data, unsigned int start_addr)
  66 {
  67         uint32_t block_count;
  68         uint32_t *buffer;
  69         uint32_t *buffer_end;
  70         uint32_t ps;
  71         uint32_t ps_mask;
  72         uint32_t stat;
  73         struct stopwatch sw;
  74
  75         block_count = 0;
  76         buffer = (uint32_t *)data->dest;
  77         ps_mask = (data->flags & DATA_FLAG_READ)
  78                 ? SDHCI_DATA_AVAILABLE : SDHCI_SPACE_AVAILABLE;
  79         stopwatch_init_msecs_expire(&sw, 100);
  80         do {
  81                 /* Stop transfers if there is an error */
  82                 stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
  83                 sdhci_writel(sdhci_ctrlr, stat, SDHCI_INT_STATUS);
  84                 if (stat & SDHCI_INT_ERROR) {
  85                         sdhc_error("Error detected in status(0x%X)!\n", stat);
  86                         return -1;
  87                 }
  88
  89                 /* Determine if the buffer is ready to move data */
  90                 ps = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
  91                 if (!(ps & ps_mask)) {
  92                         if (stopwatch_expired(&sw)) {
  93                                 sdhc_error("Transfer data timeout\n");
  94                                 return -1;
  95                         }
  96                         udelay(1);
  97                         continue;
  98                 }
  99
 100                 /* Transfer a block of data */
 101                 buffer_end = &buffer[data->blocksize >> 2];
 102                 if (data->flags == DATA_FLAG_READ)
 103                         while (buffer_end > buffer)
 104                                 *buffer++ = sdhci_readl(sdhci_ctrlr,
 105                                         SDHCI_BUFFER);
 106                 else
 107                         while (buffer_end > buffer)
 108                                 sdhci_writel(sdhci_ctrlr, *buffer++,
 109                                         SDHCI_BUFFER);
 110                 if (++block_count >= data->blocks)
 111                         break;
 112         } while (!(stat & SDHCI_INT_DATA_END));
 113         return 0;
 114 }
 115
 116 static int sdhci_send_command_bounced(struct sd_mmc_ctrlr *ctrlr,
 117         struct mmc_command *cmd, struct mmc_data *data,
 118         struct bounce_buffer *bbstate)
 119 {
 120         struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
 121         u16 mode = 0;
 122         unsigned int stat = 0;
 123         int ret = 0;
 124         u32 mask, flags;
 125         unsigned int timeout, start_addr = 0;
 126         struct stopwatch sw;
 127
 128         /* Wait max 1 s */
 129         timeout = 1000;
 130
 131         sdhci_writel(sdhci_ctrlr, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 132         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 133
 134         /* We shouldn't wait for data inhibit for stop commands, even
 135            though they might use busy signaling */
 136         if (cmd->flags & CMD_FLAG_IGNORE_INHIBIT)
 137                 mask &= ~SDHCI_DATA_INHIBIT;
 138
 139         while (sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE) & mask) {
 140                 if (timeout == 0) {
 141                         sdhc_trace("Cmd: %2d, Arg: 0x%08x, not sent\n",
 142                                         cmd->cmdidx, cmd->cmdarg);
 143                         sdhc_error("Controller never released inhibit bit(s), "
 144                                "present state %#8.8x.\n",
 145                                sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE));
 146                         return CARD_COMM_ERR;
 147                 }
 148                 timeout--;
 149                 udelay(1000);
 150         }
 151
 152         mask = SDHCI_INT_RESPONSE;
 153         if (!(cmd->resp_type & CARD_RSP_PRESENT))
 154                 flags = SDHCI_CMD_RESP_NONE;
 155         else if (cmd->resp_type & CARD_RSP_136)
 156                 flags = SDHCI_CMD_RESP_LONG;
 157         else if (cmd->resp_type & CARD_RSP_BUSY) {
 158                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 159                 mask |= SDHCI_INT_DATA_END;
 160         } else
 161                 flags = SDHCI_CMD_RESP_SHORT;
 162
 163         if (cmd->resp_type & CARD_RSP_CRC)
 164                 flags |= SDHCI_CMD_CRC;
 165         if (cmd->resp_type & CARD_RSP_OPCODE)
 166                 flags |= SDHCI_CMD_INDEX;
 167         if (data)
 168                 flags |= SDHCI_CMD_DATA;
 169
 170         /* Set Transfer mode regarding to data flag */
 171         if (data) {
 172                 sdhci_writew(sdhci_ctrlr,
 173                         SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 174                         data->blocksize), SDHCI_BLOCK_SIZE);
 175
 176                 if (data->flags == DATA_FLAG_READ)
 177                         mode |= SDHCI_TRNS_READ;
 178
 179                 if (data->blocks > 1)
 180                         mode |= SDHCI_TRNS_BLK_CNT_EN |
 181                                 SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
 182
 183                 sdhci_writew(sdhci_ctrlr, data->blocks, SDHCI_BLOCK_COUNT);
 184
 185                 if (DMA_AVAILABLE && (ctrlr->caps & DRVR_CAP_AUTO_CMD12)
 186                         && (cmd->cmdidx != MMC_CMD_AUTO_TUNING_SEQUENCE)) {
 187                         if (sdhci_setup_adma(sdhci_ctrlr, data))
 188                                 return -1;
 189                         mode |= SDHCI_TRNS_DMA;
 190                 }
 191                 sdhci_writew(sdhci_ctrlr, mode, SDHCI_TRANSFER_MODE);
 192         }
 193
 194         sdhc_trace("Cmd: %2d, Arg: 0x%08x\n", cmd->cmdidx, cmd->cmdarg);
 195         sdhci_writel(sdhci_ctrlr, cmd->cmdarg, SDHCI_ARGUMENT);
 196         sdhci_writew(sdhci_ctrlr, SDHCI_MAKE_CMD(cmd->cmdidx, flags),
 197                 SDHCI_COMMAND);
 198         sdhc_log_command_issued();
 199
 200         if (DMA_AVAILABLE && (mode & SDHCI_TRNS_DMA))
 201                 return sdhci_complete_adma(sdhci_ctrlr, cmd);
 202
 203         stopwatch_init_msecs_expire(&sw, 2550);
 204         do {
 205                 stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
 206                 if (stat & SDHCI_INT_ERROR) {
 207                         sdhc_trace("Error - IntStatus: 0x%08x\n", stat);
 208                         break;
 209                 }
 210
 211                 if (stat & SDHCI_INT_DATA_AVAIL) {
 212                         sdhci_writel(sdhci_ctrlr, stat, SDHCI_INT_STATUS);
 213                         return 0;
 214                 }
 215
 216                 /* Apply max timeout for R1b-type CMD defined in eMMC ext_csd
 217                    except for erase ones */
 218                 if (stopwatch_expired(&sw)) {
 219                         if (ctrlr->caps & DRVR_CAP_BROKEN_R1B)
 220                                 return 0;
 221                         sdhc_error(
 222                                 "Timeout for status update!  IntStatus: 0x%08x\n",
 223                                 stat);
 224                         return CARD_TIMEOUT;
 225                 }
 226         } while ((stat & mask) != mask);
 227
 228         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 229                 if (cmd->cmdidx)
 230                         sdhci_cmd_done(sdhci_ctrlr, cmd);
 231                 sdhci_writel(sdhci_ctrlr, mask, SDHCI_INT_STATUS);
 232         } else
 233                 ret = -1;
 234
 235         if (!ret && data)
 236                 ret = sdhci_transfer_data(sdhci_ctrlr, data, start_addr);
 237
 238         if (ctrlr->udelay_wait_after_cmd)
 239                 udelay(ctrlr->udelay_wait_after_cmd);
 240
 241         stat = sdhci_readl(sdhci_ctrlr, SDHCI_INT_STATUS);
 242         sdhci_writel(sdhci_ctrlr, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 243
 244         if (!ret)
 245                 return 0;
 246
 247         sdhci_reset(sdhci_ctrlr, SDHCI_RESET_CMD);
 248         sdhci_reset(sdhci_ctrlr, SDHCI_RESET_DATA);
 249         if (stat & SDHCI_INT_TIMEOUT) {
 250                 sdhc_error("CMD%d timeout, IntStatus: 0x%08x\n", cmd->cmdidx,
 251                         stat);
 252                 return CARD_TIMEOUT;
 253         }
 254
 255         sdhc_error("CMD%d failed, IntStatus: 0x%08x\n", cmd->cmdidx, stat);
 256         return CARD_COMM_ERR;
 257 }
 258
 259 __weak void sdhc_log_command(struct mmc_command *cmd)
 260 {
 261 }
 262
 263 __weak void sdhc_log_command_issued(void)
 264 {
 265 }
 266
 267 __weak void sdhc_log_response(uint32_t entries,
 268         uint32_t *response)
 269 {
 270 }
 271
 272 __weak void sdhc_log_ret(int ret)
 273 {
 274 }
 275
 276 static void sdhci_led_control(struct sd_mmc_ctrlr *ctrlr, int on)
 277 {
 278         uint8_t host_ctrl;
 279         struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
 280
 281         host_ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_HOST_CONTROL);
 282         host_ctrl &= ~SDHCI_CTRL_LED;
 283         if (on)
 284                 host_ctrl |= SDHCI_CTRL_LED;
 285         sdhci_writeb(sdhci_ctrlr, host_ctrl, SDHCI_HOST_CONTROL);
 286 }
 287
 288 static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr,
 289         struct mmc_command *cmd, struct mmc_data *data)
 290 {
 291         void *buf;
 292         unsigned int bbflags;
 293         size_t len;
 294         struct bounce_buffer *bbstate = NULL;
 295         struct bounce_buffer bbstate_val;
 296         int ret;
 297
 298         sdhc_log_command(cmd);
 299
 300         if (CONFIG(SDHCI_BOUNCE_BUFFER) && data) {
 301                 if (data->flags & DATA_FLAG_READ) {
 302                         buf = data->dest;
 303                         bbflags = GEN_BB_WRITE;
 304                 } else {
 305                         buf = (void *)data->src;
 306                         bbflags = GEN_BB_READ;
 307                 }
 308                 len = data->blocks * data->blocksize;
 309
 310                 /*
 311                  * on some platform(like rk3399 etc) need to worry about
 312                  * cache coherency, so check the buffer, if not dma
 313                  * coherent, use bounce_buffer to do DMA management.
 314                  */
 315                 if (!dma_coherent(buf)) {
 316                         bbstate = &bbstate_val;
 317                         if (bounce_buffer_start(bbstate, buf, len, bbflags)) {
 318                                 sdhc_error("Failed to get bounce buffer.\n");
 319                                 return -1;
 320                         }
 321                 }
 322         }
 323
 324         sdhci_led_control(ctrlr, 1);
 325         ret = sdhci_send_command_bounced(ctrlr, cmd, data, bbstate);
 326         sdhci_led_control(ctrlr, 0);
 327         sdhc_log_ret(ret);
 328
 329         if (CONFIG(SDHCI_BOUNCE_BUFFER) && bbstate)
 330                 bounce_buffer_stop(bbstate);
 331
 332         return ret;
 333 }
 334
 335 static int sdhci_set_clock(struct sdhci_ctrlr *sdhci_ctrlr, unsigned int clock)
 336 {
 337         struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
 338         unsigned int actual, div, clk, timeout;
 339
 340         /* Turn off the clock if requested */
 341         actual = clock;
 342         if (actual == 0) {
 343                 sdhci_writew(sdhci_ctrlr, 0, SDHCI_CLOCK_CONTROL);
 344                 sdhc_debug("SDHCI bus clock: Off\n");
 345                 return 0;
 346         }
 347
 348         /* Compute the divisor for the new clock frequency */
 349         actual = MIN(actual, ctrlr->f_max);
 350         actual = MAX(actual, ctrlr->f_min);
 351         if (ctrlr->clock_base <= actual)
 352                 div = 0;
 353         else {
 354                 /* Version 3.00 divisors must be a multiple of 2. */
 355                 if ((ctrlr->version & SDHCI_SPEC_VER_MASK)
 356                         >= SDHCI_SPEC_300) {
 357                         div = MIN(((ctrlr->clock_base + actual - 1)
 358                                 / actual), SDHCI_MAX_DIV_SPEC_300);
 359                         actual = ctrlr->clock_base / div;
 360                         div += 1;
 361                 } else {
 362                         /* Version 2.00 divisors must be a power of 2. */
 363                         for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 364                                 if ((ctrlr->clock_base / div) <= actual)
 365                                         break;
 366                         }
 367                         actual = ctrlr->clock_base / div;
 368                 }
 369                 div >>= 1;
 370         }
 371
 372         /* Set the new clock frequency */
 373         if (actual != ctrlr->bus_hz) {
 374                 /* Turn off the clock */
 375                 sdhci_writew(sdhci_ctrlr, 0, SDHCI_CLOCK_CONTROL);
 376
 377                 /* Set the new clock frequency */
 378                 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 379                 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 380                         << SDHCI_DIVIDER_HI_SHIFT;
 381                 clk |= SDHCI_CLOCK_INT_EN;
 382                 sdhci_writew(sdhci_ctrlr, clk, SDHCI_CLOCK_CONTROL);
 383
 384                 /* Display the requested clock frequency */
 385                 sdhc_debug("SDHCI bus clock: %d.%03d MHz\n",
 386                                 actual / 1000000,
 387                                 (actual / 1000) % 1000);
 388
 389                 /* Wait max 20 ms */
 390                 timeout = 20;
 391                 while (!((clk = sdhci_readw(sdhci_ctrlr, SDHCI_CLOCK_CONTROL))
 392                         & SDHCI_CLOCK_INT_STABLE)) {
 393                         if (timeout == 0) {
 394                                 sdhc_error(
 395                                         "Internal clock never stabilised.\n");
 396                                 return -1;
 397                         }
 398                         timeout--;
 399                         udelay(1000);
 400                 }
 401
 402                 clk |= SDHCI_CLOCK_CARD_EN;
 403                 sdhci_writew(sdhci_ctrlr, clk, SDHCI_CLOCK_CONTROL);
 404                 ctrlr->bus_hz = actual;
 405         }
 406         return 0;
 407 }
 408
 409 static void sdhci_set_power(struct sdhci_ctrlr *sdhci_ctrlr,
 410         unsigned short power)
 411 {
 412         struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
 413         u8 pwr = 0;
 414         u8 pwr_ctrl;
 415         const char *voltage;
 416
 417         if (power != (unsigned short)-1) {
 418                 switch (1 << power) {
 419                 case MMC_VDD_165_195:
 420                         voltage = "1.8";
 421                         pwr = SDHCI_POWER_180;
 422                         break;
 423                 case MMC_VDD_29_30:
 424                 case MMC_VDD_30_31:
 425                         voltage = "3.0";
 426                         pwr = SDHCI_POWER_300;
 427                         break;
 428                 case MMC_VDD_32_33:
 429                 case MMC_VDD_33_34:
 430                         voltage = "3.3";
 431                         pwr = SDHCI_POWER_330;
 432                         break;
 433                 }
 434         }
 435
 436         /* Determine the power state */
 437         pwr_ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_POWER_CONTROL);
 438         if (pwr == 0) {
 439                 if (pwr_ctrl & SDHCI_POWER_ON)
 440                         sdhc_debug("SDHCI voltage: Off\n");
 441                 sdhci_writeb(sdhci_ctrlr, 0, SDHCI_POWER_CONTROL);
 442                 return;
 443         }
 444
 445         /* Determine if the power has changed */
 446         if (pwr_ctrl != (pwr | SDHCI_POWER_ON)) {
 447                 sdhc_debug("SDHCI voltage: %s Volts\n", voltage);
 448
 449                 /* Select the voltage */
 450                 if (ctrlr->caps & DRVR_CAP_NO_SIMULT_VDD_AND_POWER)
 451                         sdhci_writeb(sdhci_ctrlr, pwr, SDHCI_POWER_CONTROL);
 452
 453                 /* Apply power to the SD/MMC device */
 454                 pwr |= SDHCI_POWER_ON;
 455                 sdhci_writeb(sdhci_ctrlr, pwr, SDHCI_POWER_CONTROL);
 456         }
 457 }
 458
 459 const u16 speed_driver_voltage[] = {
 460         0, /*  0: BUS_TIMING_LEGACY */
 461         0, /*  1: BUS_TIMING_MMC_HS */
 462         0, /*  2: BUS_TIMING_SD_HS */
 463         SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180, /* 3: BUS_TIMING_UHS_SDR12 */
 464         SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180, /* 4: BUS_TIMING_UHS_SDR25 */
 465         SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180, /* 5: BUS_TIMING_UHS_SDR50 */
 466         /*  6: BUS_TIMING_UHS_SDR104 */
 467         SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
 468         SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180, /* 7: BUS_TIMING_UHS_DDR50 */
 469         SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180, /* 8: BUS_TIMING_MMC_DDR52 */
 470         /*  9: BUS_TIMING_MMC_HS200 */
 471         SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
 472         /* 10: BUS_TIMING_MMC_HS400 */
 473         SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180,
 474         /* 11: BUS_TIMING_MMC_HS400ES */
 475         SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A | SDHCI_CTRL_VDD_180
 476 };
 477
 478 static void sdhci_set_uhs_signaling(struct sdhci_ctrlr *sdhci_ctrlr,
 479         uint32_t timing)
 480 {
 481         u16 ctrl_2;
 482
 483         /* Select bus speed mode, driver and VDD 1.8 volt support */
 484         ctrl_2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
 485         ctrl_2 &= ~(SDHCI_CTRL_UHS_MASK | SDHCI_CTRL_DRV_TYPE_MASK
 486                 | SDHCI_CTRL_VDD_180);
 487         if (timing < ARRAY_SIZE(speed_driver_voltage))
 488                 ctrl_2 |= speed_driver_voltage[timing];
 489         sdhci_writew(sdhci_ctrlr, ctrl_2, SDHCI_HOST_CONTROL2);
 490 }
 491
 492 static void sdhci_set_ios(struct sd_mmc_ctrlr *ctrlr)
 493 {
 494         struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
 495         u32 ctrl;
 496         u32 previous_ctrl;
 497         u32 bus_width;
 498         int version;
 499
 500         /* Set the clock frequency */
 501         if (ctrlr->bus_hz != ctrlr->request_hz)
 502                 sdhci_set_clock(sdhci_ctrlr, ctrlr->request_hz);
 503
 504         /* Switch to 1.8 volt for HS200 */
 505         if (ctrlr->caps & DRVR_CAP_1V8_VDD)
 506                 if (ctrlr->bus_hz == CLOCK_200MHZ)
 507                         sdhci_set_power(sdhci_ctrlr, MMC_VDD_165_195_SHIFT);
 508
 509         /* Determine the new bus width */
 510         bus_width = 1;
 511         ctrl = sdhci_readb(sdhci_ctrlr, SDHCI_HOST_CONTROL);
 512         previous_ctrl = ctrl;
 513         ctrl &= ~SDHCI_CTRL_4BITBUS;
 514         version = ctrlr->version & SDHCI_SPEC_VER_MASK;
 515         if (version >= SDHCI_SPEC_300)
 516                 ctrl &= ~SDHCI_CTRL_8BITBUS;
 517
 518         if ((ctrlr->bus_width == 8) && (version >= SDHCI_SPEC_300)) {
 519                 ctrl |= SDHCI_CTRL_8BITBUS;
 520                 bus_width = 8;
 521         } else if (ctrlr->bus_width == 4) {
 522                 ctrl |= SDHCI_CTRL_4BITBUS;
 523                 bus_width = 4;
 524         }
 525
 526         if (!(ctrlr->timing == BUS_TIMING_LEGACY) &&
 527             !(ctrlr->caps & DRVR_CAP_NO_HISPD_BIT))
 528                 ctrl |= SDHCI_CTRL_HISPD;
 529         else
 530                 ctrl &= ~SDHCI_CTRL_HISPD;
 531
 532         sdhci_set_uhs_signaling(sdhci_ctrlr, ctrlr->timing);
 533
 534         if (DMA_AVAILABLE) {
 535                 if (ctrlr->caps & DRVR_CAP_AUTO_CMD12) {
 536                         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 537                         if (ctrlr->caps & DRVR_CAP_DMA_64BIT)
 538                                 ctrl |= SDHCI_CTRL_ADMA64;
 539                         else
 540                                 ctrl |= SDHCI_CTRL_ADMA32;
 541                 }
 542         }
 543
 544         /* Set the new bus width */
 545         if (CONFIG(SDHC_DEBUG)
 546                 && ((ctrl ^ previous_ctrl) & (SDHCI_CTRL_4BITBUS
 547                 | ((version >= SDHCI_SPEC_300) ? SDHCI_CTRL_8BITBUS : 0))))
 548                 sdhc_debug("SDHCI bus width: %d bit%s\n", bus_width,
 549                         (bus_width != 1) ? "s" : "");
 550         sdhci_writeb(sdhci_ctrlr, ctrl, SDHCI_HOST_CONTROL);
 551 }
 552
 553 static void sdhci_tuning_start(struct sd_mmc_ctrlr *ctrlr, int retune)
 554 {
 555         uint16_t host_ctrl2;
 556         struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
 557
 558         /* Start the bus tuning */
 559         host_ctrl2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
 560         host_ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
 561         host_ctrl2 |= (retune ? SDHCI_CTRL_TUNED_CLK : 0)
 562                 | SDHCI_CTRL_EXEC_TUNING;
 563         sdhci_writew(sdhci_ctrlr, host_ctrl2, SDHCI_HOST_CONTROL2);
 564 }
 565
 566 static int sdhci_is_tuning_complete(struct sd_mmc_ctrlr *ctrlr, int *successful)
 567 {
 568         uint16_t host_ctrl2;
 569         struct sdhci_ctrlr *sdhci_ctrlr = (struct sdhci_ctrlr *)ctrlr;
 570
 571         /* Determine if the bus tuning has completed */
 572         host_ctrl2 = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_CONTROL2);
 573         *successful = ((host_ctrl2 & SDHCI_CTRL_TUNED_CLK) != 0);
 574         return ((host_ctrl2 & SDHCI_CTRL_EXEC_TUNING) == 0);
 575 }
 576
 577 /* Prepare SDHCI controller to be initialized */
 578 static int sdhci_pre_init(struct sdhci_ctrlr *sdhci_ctrlr)
 579 {
 580         struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
 581         unsigned int caps, caps_1;
 582
 583         /*
 584          * If the device needs to do anything non-standard before
 585          * sdhci initialization, run it here.
 586          */
 587         if (sdhci_ctrlr->attach) {
 588                 int rv = sdhci_ctrlr->attach(sdhci_ctrlr);
 589                 if (rv)
 590                         return rv;
 591         }
 592
 593         /* Get controller version and capabilities */
 594         ctrlr->version = sdhci_readw(sdhci_ctrlr, SDHCI_HOST_VERSION) & 0xff;
 595         caps = sdhci_readl(sdhci_ctrlr, SDHCI_CAPABILITIES);
 596         caps_1 = sdhci_readl(sdhci_ctrlr, SDHCI_CAPABILITIES_1);
 597
 598         /* Determine the supported voltages */
 599         if (caps & SDHCI_CAN_VDD_330)
 600                 ctrlr->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 601         if (caps & SDHCI_CAN_VDD_300)
 602                 ctrlr->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 603         if (caps & SDHCI_CAN_VDD_180)
 604                 ctrlr->voltages |= MMC_VDD_165_195;
 605
 606         /* Get the controller's base clock frequency */
 607         if ((ctrlr->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
 608                 ctrlr->clock_base = (caps & SDHCI_CLOCK_V3_BASE_MASK)
 609                         >> SDHCI_CLOCK_BASE_SHIFT;
 610         else
 611                 ctrlr->clock_base = (caps & SDHCI_CLOCK_BASE_MASK)
 612                         >> SDHCI_CLOCK_BASE_SHIFT;
 613         ctrlr->clock_base *= 1000000;
 614         ctrlr->f_max = ctrlr->clock_base;
 615
 616         /* Determine the controller's clock frequency range */
 617         ctrlr->f_min = 0;
 618         if ((ctrlr->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
 619                 ctrlr->f_min =
 620                         ctrlr->clock_base / SDHCI_MAX_DIV_SPEC_300;
 621         else
 622                 ctrlr->f_min =
 623                         ctrlr->clock_base / SDHCI_MAX_DIV_SPEC_200;
 624
 625         /* Determine the controller's modes of operation */
 626         ctrlr->caps |= DRVR_CAP_HS52 | DRVR_CAP_HS;
 627         if (ctrlr->clock_base >= CLOCK_200MHZ) {
 628                 ctrlr->caps |= DRVR_CAP_HS200 | DRVR_CAP_HS200_TUNING;
 629                 if (caps_1 & SDHCI_SUPPORT_HS400)
 630                         ctrlr->caps |= DRVR_CAP_HS400
 631                                 | DRVR_CAP_ENHANCED_STROBE;
 632         }
 633
 634         /* Determine the bus widths the controller supports */
 635         ctrlr->caps |= DRVR_CAP_4BIT;
 636         if (caps & SDHCI_CAN_DO_8BIT)
 637                 ctrlr->caps |= DRVR_CAP_8BIT;
 638
 639         /* Determine the controller's DMA support */
 640         if (caps & SDHCI_CAN_DO_ADMA2)
 641                 ctrlr->caps |= DRVR_CAP_AUTO_CMD12;
 642         if (DMA_AVAILABLE && (caps & SDHCI_CAN_64BIT))
 643                 ctrlr->caps |= DRVR_CAP_DMA_64BIT;
 644
 645         /* Specify the modes that the driver stack supports */
 646         ctrlr->caps |= DRVR_CAP_HC;
 647
 648         /* Let the SOC adjust the configuration to handle controller quirks */
 649         soc_sd_mmc_controller_quirks(&sdhci_ctrlr->sd_mmc_ctrlr);
 650         if (ctrlr->clock_base == 0) {
 651                 sdhc_error("Hardware doesn't specify base clock frequency\n");
 652                 return -1;
 653         }
 654         if (!ctrlr->f_max)
 655                 ctrlr->f_max = ctrlr->clock_base;
 656
 657         /* Display the results */
 658         sdhc_trace("0x%08x: ctrlr->caps\n", ctrlr->caps);
 659         sdhc_trace("%d.%03d MHz: ctrlr->clock_base\n",
 660                 ctrlr->clock_base / 1000000,
 661                 (ctrlr->clock_base / 1000) % 1000);
 662         sdhc_trace("%d.%03d MHz: ctrlr->f_max\n",
 663                 ctrlr->f_max / 1000000,
 664                 (ctrlr->f_max / 1000) % 1000);
 665         sdhc_trace("%d.%03d MHz: ctrlr->f_min\n",
 666                 ctrlr->f_min / 1000000,
 667                 (ctrlr->f_min / 1000) % 1000);
 668         sdhc_trace("0x%08x: ctrlr->voltages\n", ctrlr->voltages);
 669
 670         sdhci_reset(sdhci_ctrlr, SDHCI_RESET_ALL);
 671
 672         return 0;
 673 }
 674
 675 __weak void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr
 676         *ctrlr)
 677 {
 678 }
 679
 680 static int sdhci_init(struct sdhci_ctrlr *sdhci_ctrlr)
 681 {
 682         struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
 683         int rv;
 684
 685         /* Only initialize the controller upon reset or card insertion */
 686         if (ctrlr->initialized)
 687                 return 0;
 688
 689         sdhc_debug("SDHCI Controller Base Address: %p\n",
 690                         sdhci_ctrlr->ioaddr);
 691
 692         rv = sdhci_pre_init(sdhci_ctrlr);
 693         if (rv)
 694                 return rv; /* The error has been already reported */
 695
 696         sdhci_set_power(sdhci_ctrlr, __fls(ctrlr->voltages));
 697
 698         if (ctrlr->caps & DRVR_CAP_NO_CD) {
 699                 unsigned int status;
 700
 701                 sdhci_writel(sdhci_ctrlr, SDHCI_CTRL_CD_TEST_INS
 702                         | SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
 703
 704                 status = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
 705                 while ((!(status & SDHCI_CARD_PRESENT)) ||
 706                     (!(status & SDHCI_CARD_STATE_STABLE)) ||
 707                     (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
 708                         status = sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE);
 709         }
 710
 711         /* Enable only interrupts served by the SD controller */
 712         sdhci_writel(sdhci_ctrlr, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 713                      SDHCI_INT_ENABLE);
 714         /* Mask all sdhci interrupt sources */
 715         sdhci_writel(sdhci_ctrlr, 0x0, SDHCI_SIGNAL_ENABLE);
 716
 717         /* Set timeout to maximum, shouldn't happen if everything's right. */
 718         sdhci_writeb(sdhci_ctrlr, 0xe, SDHCI_TIMEOUT_CONTROL);
 719
 720         mdelay(10);
 721         ctrlr->initialized = 1;
 722         return 0;
 723 }
 724
 725 static int sdhci_update(struct sdhci_ctrlr *sdhci_ctrlr)
 726 {
 727         struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
 728
 729         if (ctrlr->caps & DRVR_CAP_REMOVABLE) {
 730                 int present = (sdhci_readl(sdhci_ctrlr, SDHCI_PRESENT_STATE) &
 731                                SDHCI_CARD_PRESENT) != 0;
 732
 733                 if (!present) {
 734                         /* A card was present indicate the controller needs
 735                          * initialization on the next call.
 736                          */
 737                         ctrlr->initialized = 0;
 738                         return 0;
 739                 }
 740         }
 741
 742         /* A card is present, get it ready. */
 743         if (sdhci_init(sdhci_ctrlr))
 744                 return -1;
 745         return 0;
 746 }
 747
 748 void sdhci_update_pointers(struct sdhci_ctrlr *sdhci_ctrlr)
 749 {
 750         struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
 751
 752         /* Update the routine pointers */
 753         ctrlr->send_cmd = &sdhci_send_command;
 754         ctrlr->set_ios = &sdhci_set_ios;
 755         ctrlr->tuning_start = &sdhci_tuning_start;
 756         ctrlr->is_tuning_complete = &sdhci_is_tuning_complete;
 757 }
 758
 759 int add_sdhci(struct sdhci_ctrlr *sdhci_ctrlr)
 760 {
 761         struct sd_mmc_ctrlr *ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
 762
 763         sdhci_update_pointers(sdhci_ctrlr);
 764
 765         /* TODO(vbendeb): check if SDHCI spec allows to retrieve this value. */
 766         ctrlr->b_max = 65535;
 767
 768         /* Initialize the SDHC controller */
 769         return sdhci_update(sdhci_ctrlr);
 770 }