src/device/azalia_device.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/azalia_device.h>
   7 #include <device/mmio.h>
   8 #include <delay.h>
   9 #include <timer.h>
  10 #include <types.h>
  11
  12 static enum cb_err azalia_set_bits(void *port, u32 mask, u32 val)
  13 {
  14         struct stopwatch sw;
  15         u32 reg32;
  16
  17         /* Write (val & mask) to port */
  18         val &= mask;
  19         reg32 = read32(port);
  20         reg32 &= ~mask;
  21         reg32 |= val;
  22         write32(port, reg32);
  23
  24         /* Wait for readback of register to match what was just written to it */
  25         stopwatch_init_msecs_expire(&sw, 50);
  26         do {
  27                 /* Wait 1ms based on BKDG wait time */
  28                 mdelay(1);
  29                 reg32 = read32(port);
  30                 reg32 &= mask;
  31         } while ((reg32 != val) && !stopwatch_expired(&sw));
  32
  33         /* Timeout occurred */
  34         if (stopwatch_expired(&sw))
  35                 return CB_ERR;
  36         return CB_SUCCESS;
  37 }
  38
  39 enum cb_err azalia_enter_reset(u8 *base)
  40 {
  41         /* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
  42         return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
  43 }
  44
  45 enum cb_err azalia_exit_reset(u8 *base)
  46 {
  47         /* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
  48         return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST);
  49 }
  50
  51 static u16 codec_detect(u8 *base)
  52 {
  53         struct stopwatch sw;
  54         u16 reg16;
  55
  56         if (azalia_exit_reset(base) != CB_SUCCESS)
  57                 goto no_codec;
  58
  59         /*
  60          * In the HD Audio Specification Rev. 1.0a, every bitfield in the GCAP
  61          * register is RO (Read Only). However, it is known that in some Intel
  62          * PCHs (e.g 6-series and 7-series, documents 324645 and 326776), some
  63          * of the bitfields in the GCAP register are R/WO (Read / Write Once).
  64          * GCAP is RO on 5-series PCHs; 8-series and 9-series PCHs have a lock
  65          * bit for GCAP elsewhere.
  66          *
  67          * Lock GCAP by reading GCAP and writing back the same value. This has
  68          * no effect on platforms that implement GCAP as a RO register or lock
  69          * GCAP through a different mechanism.
  70          */
  71         write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
  72
  73         /* clear STATESTS bits (BAR + 0x0e)[14:0] */
  74         reg16 = read16(base + HDA_STATESTS_REG);
  75         reg16 |= 0x7fff;
  76         write16(base + HDA_STATESTS_REG, reg16);
  77
  78         /* Wait for readback of register to
  79          * match what was just written to it
  80          */
  81         stopwatch_init_msecs_expire(&sw, 50);
  82         do {
  83                 /* Wait 1ms based on BKDG wait time */
  84                 mdelay(1);
  85                 reg16 = read16(base + HDA_STATESTS_REG);
  86         } while ((reg16 != 0) && !stopwatch_expired(&sw));
  87
  88         /* Timeout occurred */
  89         if (stopwatch_expired(&sw))
  90                 goto no_codec;
  91
  92         if (azalia_enter_reset(base) != CB_SUCCESS)
  93                 goto no_codec;
  94
  95         if (azalia_exit_reset(base) != CB_SUCCESS)
  96                 goto no_codec;
  97
  98         /* Read in Codec location (BAR + 0x0e)[14:0] */
  99         reg16 = read16(base + HDA_STATESTS_REG);
 100         reg16 &= 0x7fff;
 101         if (!reg16)
 102                 goto no_codec;
 103
 104         return reg16;
 105
 106 no_codec:
 107         /* Codec Not found */
 108         azalia_enter_reset(base);
 109         printk(BIOS_DEBUG, "azalia_audio: no codec!\n");
 110         return 0;
 111 }
 112
 113 /*
 114  * Find a specific entry within a verb table
 115  *
 116  * @param verb_table:           verb table data
 117  * @param verb_table_bytes:     verb table size in bytes
 118  * @param viddid:               vendor/device to search for
 119  * @param verb:                 pointer to entry within table
 120  *
 121  * Returns size of the entry within the verb table,
 122  * Returns 0 if the entry is not found
 123  *
 124  * The HDA verb table is composed of dwords. A set of 4 dwords is
 125  * grouped together to form a "jack" descriptor.
 126  *   Bits 31:28 - Codec Address
 127  *   Bits 27:20 - NID
 128  *   Bits 19:8  - Verb ID
 129  *   Bits  7:0  - Payload
 130  *
 131  * coreboot groups different codec verb tables into a single table
 132  * and prefixes each with a specific header consisting of 3
 133  * dword entries:
 134  *   1 - Codec Vendor/Device ID
 135  *   2 - Subsystem ID
 136  *   3 - Number of jacks (groups of 4 dwords) for this codec
 137  */
 138 u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb)
 139 {
 140         int idx = 0;
 141
 142         while (idx < (verb_table_bytes / sizeof(u32))) {
 143                 /* Header contains the number of jacks, aka groups of 4 dwords */
 144                 u32 verb_size = 4 * verb_table[idx + 2];
 145                 if (verb_table[idx] != viddid) {
 146                         idx += verb_size + 3;   // skip verb + header
 147                         continue;
 148                 }
 149                 *verb = &verb_table[idx + 3];
 150                 return verb_size;
 151         }
 152
 153         /* Not all codecs need to load another verb */
 154         return 0;
 155 }
 156
 157 /*
 158  * Wait 50usec for the controller to indicate it is ready.
 159  */
 160 static int wait_for_ready(u8 *base)
 161 {
 162         struct stopwatch sw;
 163         /* Use a 50 usec timeout - the Linux kernel uses the same duration */
 164         stopwatch_init_usecs_expire(&sw, 50);
 165
 166         while (!stopwatch_expired(&sw)) {
 167                 u32 reg32 = read32(base + HDA_ICII_REG);
 168                 if (!(reg32 & HDA_ICII_BUSY))
 169                         return 0;
 170                 udelay(1);
 171         }
 172
 173         return -1;
 174 }
 175
 176 /*
 177  * Wait for the codec to indicate that it accepted the previous command.
 178  * No response would imply that the codec is non-operative.
 179  */
 180 static int wait_for_valid(u8 *base)
 181 {
 182         struct stopwatch sw;
 183         u32 reg32;
 184
 185         /* Send the verb to the codec */
 186         reg32 = read32(base + HDA_ICII_REG);
 187         reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
 188         write32(base + HDA_ICII_REG, reg32);
 189
 190         /*
 191          * The timeout is never reached when the codec is functioning properly.
 192          * Using a small timeout value can result in spurious errors with some
 193          * codecs, e.g. a codec that is slow to respond but operates correctly.
 194          * When a codec is non-operative, the timeout is only reached once per
 195          * verb table, thus the impact on booting time is relatively small. So,
 196          * use a reasonably long enough timeout to cover all possible cases.
 197          */
 198         stopwatch_init_msecs_expire(&sw, 1);
 199         while (!stopwatch_expired(&sw)) {
 200                 reg32 = read32(base + HDA_ICII_REG);
 201                 if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID)
 202                         return 0;
 203                 udelay(1);
 204         }
 205
 206         /*
 207          * HDA spec 1.0a "3.4.3 Offset 68h: Immediate Command Status"
 208          * tells us to clear the busy bit explicitly, then poll until
 209          * the controller is ready.
 210          */
 211         write32(base + HDA_ICII_REG, 0);
 212         if (wait_for_ready(base) < 0) {
 213                 printk(BIOS_WARNING, "azalia_audio: controller is unresponsive.\n");
 214                 return -2;
 215         }
 216         return -1;
 217 }
 218
 219 static int azalia_write_verb(u8 *base, u32 verb)
 220 {
 221         if (wait_for_ready(base) < 0)
 222                 return -1;
 223
 224         write32(base + HDA_IC_REG, verb);
 225
 226         return wait_for_valid(base);
 227 }
 228
 229 int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size)
 230 {
 231         if (!verbs)
 232                 return 0;
 233
 234         for (u32 i = 0; i < verb_size; i++) {
 235                 if (azalia_write_verb(base, verbs[i]) < 0)
 236                         return -1;
 237         }
 238         return 0;
 239 }
 240
 241 __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
 242 {
 243 }
 244
 245 static bool codec_is_operative(u8 *base, const int addr)
 246 {
 247         if (wait_for_ready(base) < 0) {
 248                 printk(BIOS_WARNING, "azalia_audio: controller not ready\n");
 249                 return false;
 250         }
 251
 252         const u32 reg32 = (addr << 28) | 0x000f0000;
 253         write32(base + HDA_IC_REG, reg32);
 254
 255         if (wait_for_valid(base) < 0) {
 256                 printk(BIOS_NOTICE, "azalia_audio: codec #%d doesn't respond\n", addr);
 257                 return false;
 258         }
 259         return true;
 260 }
 261
 262 void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes)
 263 {
 264         const u32 viddid = read32(base + HDA_IR_REG);
 265         const u32 *verb;
 266         u32 verb_size;
 267
 268         printk(BIOS_DEBUG, "azalia_audio: initializing codec #%d...\n", addr);
 269         printk(BIOS_DEBUG, "azalia_audio:  - vendor/device id: 0x%08x\n", viddid);
 270
 271         verb_size = azalia_find_verb(verb_table, verb_table_bytes, viddid, &verb);
 272
 273         if (verb_size == 0) {
 274                 printk(BIOS_DEBUG, "azalia_audio:  - no verb!\n");
 275                 return;
 276         }
 277         printk(BIOS_DEBUG, "azalia_audio:  - verb size: %u\n", verb_size);
 278
 279         if (azalia_program_verb_table(base, verb, verb_size) < 0)
 280                 printk(BIOS_DEBUG, "azalia_audio:  - verb not loaded\n");
 281         else
 282                 printk(BIOS_DEBUG, "azalia_audio:  - verb loaded\n");
 283
 284         mainboard_azalia_program_runtime_verbs(base, viddid);
 285 }
 286
 287 static bool codec_can_init(const u16 codec_mask, u8 *base, const int addr)
 288 {
 289         return codec_mask & (1 << addr) && codec_is_operative(base, addr);
 290 }
 291
 292 void azalia_codecs_init(u8 *base, u16 codec_mask)
 293 {
 294         for (int i = AZALIA_MAX_CODECS - 1; i >= 0; i--) {
 295                 if (codec_can_init(codec_mask, base, i))
 296                         azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
 297         }
 298
 299         azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size);
 300 }
 301
 302 void azalia_audio_init(struct device *dev)
 303 {
 304         u8 *base;
 305         struct resource *res;
 306         u16 codec_mask;
 307
 308         res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 309         if (!res)
 310                 return;
 311
 312         // NOTE this will break as soon as the azalia_audio gets a bar above 4G.
 313         // Is there anything we can do about it?
 314         base = res2mmio(res, 0, 0);
 315         printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
 316         codec_mask = codec_detect(base);
 317
 318         if (codec_mask) {
 319                 printk(BIOS_DEBUG, "azalia_audio: codec_mask = 0x%02x\n", codec_mask);
 320                 azalia_codecs_init(base, codec_mask);
 321         }
 322 }
 323
 324 struct device_operations default_azalia_audio_ops = {
 325         .read_resources         = pci_dev_read_resources,
 326         .set_resources          = pci_dev_set_resources,
 327         .enable_resources       = pci_dev_enable_resources,
 328         .init                   = azalia_audio_init,
 329         .ops_pci                = &pci_dev_ops_pci,
 330 };