src/device/dram/ddr5.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/dram/ddr5.h>
   6 #include <memory_info.h>
   7 #include <types.h>
   8
   9 enum ddr5_speed_grade {
  10         DDR5_1333,
  11         DDR5_1600,
  12         DDR5_1866,
  13         DDR5_2133,
  14         DDR5_2400,
  15         DDR5_2667,
  16         DDR5_2933,
  17         DDR5_3200,
  18         DDR5_3733,
  19         DDR5_4267,
  20         DDR5_4800,
  21         DDR5_5500,
  22         DDR5_6000,
  23         DDR5_6400,
  24 };
  25
  26 struct ddr5_speed_attr {
  27         uint32_t min_clock_mhz; // inclusive
  28         uint32_t max_clock_mhz; // inclusive
  29         uint32_t reported_mts;
  30 };
  31
  32 /**
  33  * (LP)DDR5 speed attributes derived from JEDEC JESD79-5B, JESD209-5B and industry norms
  34  *
  35  * min_clock_mhz = previous max speed + 1
  36  * max_clock_mhz = 50% of speed grade, +/- 1
  37  * reported_mts  = Standard reported DDR5 speed in MT/s
  38  *                 May be slightly less than the actual max MT/s
  39  */
  40 static const struct ddr5_speed_attr ddr5_speeds[] = {
  41         [DDR5_1333] = {
  42                 .min_clock_mhz = 10,
  43                 .max_clock_mhz = 667,
  44                 .reported_mts = 1333,
  45         },
  46         [DDR5_1600] = {
  47                 .min_clock_mhz = 668,
  48                 .max_clock_mhz = 800,
  49                 .reported_mts = 1600,
  50         },
  51         [DDR5_1866] = {
  52                 .min_clock_mhz = 801,
  53                 .max_clock_mhz = 933,
  54                 .reported_mts = 1866,
  55         },
  56         [DDR5_2133] = {
  57                 .min_clock_mhz = 934,
  58                 .max_clock_mhz = 1067,
  59                 .reported_mts = 2133,
  60         },
  61         [DDR5_2400] = {
  62                 .min_clock_mhz = 1068,
  63                 .max_clock_mhz = 1200,
  64                 .reported_mts = 2400,
  65         },
  66         [DDR5_2667] = {
  67                 .min_clock_mhz = 1201,
  68                 .max_clock_mhz = 1333,
  69                 .reported_mts = 2667,
  70         },
  71         [DDR5_2933] = {
  72                 .min_clock_mhz = 1334,
  73                 .max_clock_mhz = 1467,
  74                 .reported_mts = 2933,
  75         },
  76         [DDR5_3200] = {
  77                 .min_clock_mhz = 1468,
  78                 .max_clock_mhz = 1600,
  79                 .reported_mts = 3200,
  80         },
  81         [DDR5_3733] = {
  82                 .min_clock_mhz = 1601,
  83                 .max_clock_mhz = 1866,
  84                 .reported_mts = 3733
  85         },
  86         [DDR5_4267] = {
  87                 .min_clock_mhz = 1867,
  88                 .max_clock_mhz = 2133,
  89                 .reported_mts = 4267
  90         },
  91         [DDR5_4800] = {
  92                 .min_clock_mhz = 2134,
  93                 .max_clock_mhz = 2400,
  94                 .reported_mts = 4800
  95         },
  96         [DDR5_5500] = {
  97                 .min_clock_mhz = 2401,
  98                 .max_clock_mhz = 2750,
  99                 .reported_mts = 5500
 100         },
 101         [DDR5_6000] = {
 102                 .min_clock_mhz = 2751,
 103                 .max_clock_mhz = 3000,
 104                 .reported_mts = 6000
 105         },
 106         [DDR5_6400] = {
 107                 .min_clock_mhz = 3001,
 108                 .max_clock_mhz = 3200,
 109                 .reported_mts = 6400
 110         },
 111 };
 112
 113 /**
 114  * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s
 115  */
 116 uint16_t ddr5_speed_mhz_to_reported_mts(uint16_t speed_mhz)
 117 {
 118         for (enum ddr5_speed_grade speed = 0; speed < ARRAY_SIZE(ddr5_speeds); speed++) {
 119                 const struct ddr5_speed_attr *speed_attr = &ddr5_speeds[speed];
 120                 if (speed_mhz >= speed_attr->min_clock_mhz &&
 121                     speed_mhz <= speed_attr->max_clock_mhz) {
 122                         return speed_attr->reported_mts;
 123                 }
 124         }
 125         printk(BIOS_ERR, "DDR5 speed of %d MHz is out of range\n", speed_mhz);
 126         return 0;
 127 }