src/mainboard/google/brya/variants/anraggar/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A7  : NC ==> LTE_Present */
  11         PAD_CFG_GPI(GPP_A7, NONE, DEEP),
  12         /* A8  : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
  13         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  14         /* A11 : GPP_A11 ==> EN_SPK_PA */
  15         PAD_CFG_GPO(GPP_A11, 0, DEEP),
  16         /* A18 : NC ==> HDMI_HPD_SRC*/
  17         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  18
  19         /* A20 : DDSP_HPD2 ==> NC */
  20         PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
  21         /* A21 : GPP_A21 ==> NC */
  22         PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
  23         /* A22 : GPP_A22 ==> NC */
  24         PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
  25
  26         /* B5  : I2C2_SDA ==> MIPI_WCAM_SDA */
  27         PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
  28         /* B6  : I2C2_SCL ==> MIPI_WCAM_SCL */
  29         PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
  30
  31         /* B11 : NC ==> EN_PP3300_WLAN_X*/
  32         PAD_CFG_GPO(GPP_B11, 0, DEEP),
  33
  34         /* D6 : NC ==> WWAN_PWR_ENABLE */
  35         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  36         /* D8  : SRCCLKREQ3# ==> NC */
  37         PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
  38         /* D13 : NC ==> EN_PP1800_WCAM_X */
  39         PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG),
  40
  41         /* E20 : DDP2_CTRLCLK ==> NC */
  42         PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
  43         /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
  44         PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
  45
  46         /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
  47         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
  48         /* H23 : WWAN_SAR_DETECT_ODL */
  49         PAD_CFG_GPO(GPP_H23, 1, DEEP),
  50
  51         /* F11 : NC ==> WWAN_PWR_ON */
  52         PAD_CFG_GPO_LOCK(GPP_F11, 1, LOCK_CONFIG),
  53         /* F12 : GSXDOUT ==> WWAN_RST_L */
  54         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  55         /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
  56         PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_BOTH),
  57         /* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */
  58         PAD_CFG_GPO(GPP_F18, 0, DEEP),
  59         /* F23 : V1P05_CTRL ==> NC*/
  60         PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
  61
  62
  63         /* H12 : UART0_RTS# ==> NC*/
  64         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  65         /* H13 : UART0_CTS# ==> NC */
  66         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
  67         /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
  68         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
  69         /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
  70         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
  71
  72         /* R6 : DMIC_CLK_A_1A ==> NC */
  73         PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
  74         /* R7 : DMIC_DATA_1A ==> NC */
  75         PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
  76
  77         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
  78         /* BT_I2S_BCLK */
  79         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
  80         /* BT_I2S_SYNC */
  81         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
  82         /* BT_I2S_SDO */
  83         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
  84         /* BT_I2S_SDI */
  85         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
  86         /* SSP2_SCLK */
  87         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
  88         /* SSP2_SFRM */
  89         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
  90         /* SSP_TXD */
  91         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
  92         /* SSP_RXD */
  93         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
  94 };
  95
  96 /* Early pad configuration in bootblock */
  97 static const struct pad_config early_gpio_table[] = {
  98         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
  99         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 100         /* C1  : SMBDATA ==> TCHSCR_RST_L */
 101         PAD_CFG_GPO(GPP_C1, 1, DEEP),
 102
 103         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 104         PAD_CFG_GPO(GPP_H20, 0, DEEP),
 105         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 106         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 107         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 108         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 109
 110         /* F11 : NC ==> WWAN_PWR_ON */
 111         PAD_CFG_GPO(GPP_F11, 1, DEEP),
 112         /* F12 : GSXDOUT ==> WWAN_RST_L */
 113         PAD_CFG_GPO(GPP_F12, 0, DEEP),
 114         /* D6 : NC ==> WWAN_PWR_ENABLE */
 115         PAD_CFG_GPO(GPP_D6, 1, DEEP),
 116
 117         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 118         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 119         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 120         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 121
 122         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 123         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 124         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 125         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 126 };
 127
 128 static const struct pad_config romstage_gpio_table[] = {
 129         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 130         PAD_CFG_GPO(GPP_H20, 1, DEEP),
 131 };
 132
 133 const struct pad_config *variant_gpio_override_table(size_t *num)
 134 {
 135         *num = ARRAY_SIZE(override_gpio_table);
 136         return override_gpio_table;
 137 }
 138
 139 const struct pad_config *variant_early_gpio_table(size_t *num)
 140 {
 141         *num = ARRAY_SIZE(early_gpio_table);
 142         return early_gpio_table;
 143 }
 144
 145 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 146 {
 147         *num = ARRAY_SIZE(romstage_gpio_table);
 148         return romstage_gpio_table;
 149 }