mb/google/brya/var/orisa: Update Type C DisplayPort HPD Configuration
[coreboot2.git] / src / mainboard / google / brya / variants / banshee / memory.c
blob125e90902ea37647ac5040758058f274aa0916e7
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/variants.h>
4 #include <soc/romstage.h>
6 static const struct mb_cfg ddr4_mem_config = {
7 .type = MEM_TYPE_DDR4,
9 .rcomp = {
10 /* Baseboard uses only 100ohm Rcomp resistors */
11 .resistor = 100,
13 /* Baseboard Rcomp target values */
14 .targets = {50, 20, 25, 25, 25},
17 .LpDdrDqDqsReTraining = 1,
19 .ect = 1, /* Early Command Training */
21 .UserBd = BOARD_TYPE_MOBILE,
24 const struct mb_cfg *variant_memory_params(void)
26 return &ddr4_mem_config;
29 bool variant_is_half_populated(void)
31 return false;
34 void variant_get_spd_info(struct mem_spd *spd_info)
36 spd_info->topo = MEM_TOPO_DIMM_MODULE;
37 spd_info->smbus[0].addr_dimm[0] = 0x50;
38 spd_info->smbus[1].addr_dimm[0] = 0x52;