src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb

   1 fw_config
   2         field AUDIO_CONFIG 28
   3                 option AMP_GPIO                 0
   4                 option AMP_RT5650               1
   5         end
   6         field SD_BOOT 29
   7                 option SD_BOOT_ENABLE           0
   8                 option SD_BOOT_DISABLE          1
   9         end
  10         field STORAGE 30 31
  11                 option STORAGE_EMMC             0
  12                 option STORAGE_NVME             1
  13                 option STORAGE_UFS              2
  14                 option STORAGE_UNKNOWN          3
  15         end
  16 end
  17
  18 chip soc/intel/alderlake
  19
  20         # GPE configuration
  21         register "pmc_gpe0_dw0" = "GPP_A"
  22         register "pmc_gpe0_dw1" = "GPP_H"
  23         register "pmc_gpe0_dw2" = "GPP_F"
  24
  25         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  26         register "gen1_dec" = "0x00fc0801"
  27         register "gen2_dec" = "0x000c0201"
  28         # EC memory map range is 0x900-0x9ff
  29         register "gen3_dec" = "0x00fc0901"
  30
  31         # S0ix enable
  32         register "s0ix_enable" = "true"
  33
  34         # DPTF enable
  35         register "dptf_enable" = "1"
  36
  37         register "tcc_offset" = "10"     # TCC of 90
  38
  39         # Enable CNVi BT
  40         register "cnvi_bt_core" = "true"
  41
  42         # eMMC HS400
  43         register "emmc_enable_hs400_mode" = "true"
  44
  45         #eMMC DLL tuning parameters
  46         #Adding the intermediate eMMC DLL tuning override values
  47         #TODO SoC implementation with the finalized verified values from EV Team
  48         register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
  49         register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
  50         register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
  51         register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D3C"
  52         register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10049"
  53         register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
  54
  55         register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB2_C0
  56         register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # USB2_C1
  57         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"     # USB2_A0
  58         register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"     # USB2_A1
  59         register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 Camera
  60
  61         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
  62         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
  63
  64         register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
  65         register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
  66
  67         register "serial_io_i2c_mode" = "{
  68                 [PchSerialIoIndexI2C0] = PchSerialIoPci,
  69                 [PchSerialIoIndexI2C1] = PchSerialIoPci,
  70                 [PchSerialIoIndexI2C2] = PchSerialIoPci,
  71                 [PchSerialIoIndexI2C3] = PchSerialIoPci,
  72                 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
  73                 [PchSerialIoIndexI2C5] = PchSerialIoPci,
  74         }"
  75
  76         register "serial_io_gspi_mode" = "{
  77                 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
  78                 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
  79         }"
  80
  81         register "serial_io_uart_mode" = "{
  82                 [PchSerialIoIndexUART0] = PchSerialIoPci,
  83                 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
  84                 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
  85         }"
  86
  87         # HD Audio
  88         register "pch_hda_dsp_enable" = "1"
  89         register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
  90         register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
  91         register "pch_hda_idisp_codec_enable" = "1"
  92
  93         # FIXME: To be enabled in future based on PNP impact data.
  94         # Disable Package C-state demotion for nissa baseboard.
  95         register "disable_package_c_state_demotion" = "true"
  96
  97         # Vccin Aux Imon Iccmax, follow RDC#646929 Power Map requirement
  98         register "vccin_aux_imon_iccmax" = "PD_TIER_VOLUME" # 27A
  99
 100         # Intel Common SoC Config
 101         #+-------------------+---------------------------+
 102         #| Field             |  Value                    |
 103         #+-------------------+---------------------------+
 104         #| I2C0              | TPM. Early init is        |
 105         #|                   | required to set up a BAR  |
 106         #|                   | for TPM communication     |
 107         #| I2C1              | Touchscreen               |
 108         #| I2C2              | Sub-board(PSensor)/WCAM   |
 109         #| I2C3              | Audio                     |
 110         #| I2C5              | Trackpad                  |
 111         #+-------------------+---------------------------+
 112         register "common_soc_config" = "{
 113                 .i2c[0] = {
 114                         .early_init = 1,
 115                         .speed = I2C_SPEED_FAST_PLUS,
 116                         .speed_config[0] = {
 117                                 .speed = I2C_SPEED_FAST_PLUS,
 118                                 .scl_lcnt = 55,
 119                                 .scl_hcnt = 30,
 120                                 .sda_hold = 7,
 121                         }
 122                 },
 123                 .i2c[1] = {
 124                         .speed = I2C_SPEED_FAST,
 125                         .speed_config[0] = {
 126                                 .speed = I2C_SPEED_FAST,
 127                                 .scl_lcnt = 158,
 128                                 .scl_hcnt = 79,
 129                                 .sda_hold = 7,
 130                         }
 131                 },
 132                 .i2c[2] = {
 133                         .speed = I2C_SPEED_FAST,
 134                         .speed_config[0] = {
 135                                 .speed = I2C_SPEED_FAST,
 136                                 .scl_lcnt = 158,
 137                                 .scl_hcnt = 79,
 138                                 .sda_hold = 7,
 139                         }
 140                 },
 141                 .i2c[3] = {
 142                         .speed = I2C_SPEED_FAST,
 143                         .speed_config[0] = {
 144                                 .speed = I2C_SPEED_FAST,
 145                                 .scl_lcnt = 158,
 146                                 .scl_hcnt = 79,
 147                                 .sda_hold = 7,
 148                         }
 149                 },
 150                 .i2c[5] = {
 151                         .speed = I2C_SPEED_FAST,
 152                         .speed_config[0] = {
 153                                 .speed = I2C_SPEED_FAST,
 154                                 .scl_lcnt = 158,
 155                                 .scl_hcnt = 79,
 156                                 .sda_hold = 7,
 157                         }
 158                 },
 159         }"
 160
 161         device domain 0 on
 162                 # The timing values can be derived from datasheet of display panel
 163                 # You can use EDID string to identify the type of display on the board
 164                 # use below command to get display info from EDID
 165                 # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
 166
 167                 # refer to display PRM document (Volume 2b: Command Reference: Registers)
 168                 # for more info on display control registers
 169                 # https://01.org/linuxgraphics/documentation/hardware-specification-prms
 170                 #+-----------------------------+---------------------------------------+-----+
 171                 #| Intel docs                  | devicetree.cb                         | eDP |
 172                 #+-----------------------------+---------------------------------------+-----+
 173                 #| Power up delay              | `gpu_panel_power_up_delay`            | T3  |
 174                 #+-----------------------------+---------------------------------------+-----+
 175                 #| Power on to backlight on    | `gpu_panel_power_backlight_on_delay`  | T7  |
 176                 #+-----------------------------+---------------------------------------+-----+
 177                 #| Power Down delay            | `gpu_panel_power_down_delay`          | T10 |
 178                 #+-----------------------------+---------------------------------------+-----+
 179                 #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9  |
 180                 #+-----------------------------+---------------------------------------+-----+
 181                 #| Power Cycle Delay           | `gpu_panel_power_cycle_delay`         | T12 |
 182                 #+-----------------------------+---------------------------------------+-----+
 183                 device ref igpu on
 184                         register "panel_cfg" = "{
 185                             .up_delay_ms = 200,
 186                             .down_delay_ms = 50,
 187                             .cycle_delay_ms = 500,
 188                             .backlight_on_delay_ms = 1,
 189                             .backlight_off_delay_ms = 200,
 190                             .backlight_pwm_hz = 200,
 191                         }"
 192                         register "gfx" = "GMA_DEFAULT_PANEL(0)"
 193                 end
 194                 device ref dtt on end
 195                 device ref tcss_xhci on end
 196                 device ref xhci on end
 197                 device ref shared_sram on end
 198                 device ref cnvi_wifi on
 199                         chip drivers/wifi/generic
 200                                 register "wake" = "GPE0_PME_B0"
 201                                 register "add_acpi_dma_property" = "true"
 202                                 device generic 0 on end
 203                         end
 204                 end
 205                 device ref i2c0 on
 206                         chip drivers/i2c/tpm
 207                                 register "hid" = ""GOOG0005""
 208                                 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
 209                                 device i2c 50 on end
 210                         end
 211                 end
 212                 device ref heci1 on end
 213                 device ref emmc on end
 214                 device ref pcie_rp7 on
 215                         # Enable SD Card PCIE 7 using clk 3
 216                         register "pch_pcie_rp[PCH_RP(7)]" = "{
 217                                 .clk_src = 3,
 218                                 .clk_req = 3,
 219                                 .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
 220                         }"
 221                         chip soc/intel/common/block/pcie/rtd3
 222                                 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
 223                                 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
 224                                 register "srcclk_pin" = "3"
 225                                 device generic 0 on end
 226                         end
 227                 end     #PCIE7 SD card
 228                 device ref uart0 on end
 229                 device ref pch_espi on
 230                         chip ec/google/chromeec
 231                                 device pnp 0c09.0 on end
 232                         end
 233                 end
 234                 device ref hda on end
 235         end
 236 end