src/mainboard/google/brya/variants/craask/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage for craask */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A8  : WWAN_RF_DISABLE_ODL */
  11         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  12         /* B4  : SSD_PERST_L */
  13         PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
  14         /* D6  : WWAN_EN */
  15         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  16         /* D7  : SRCCLKREQ2# ==> SSD_CLKREQ_ODL */
  17         PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
  18         /* D11 : EN_PP3300_SSD */
  19         PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
  20         /* E17 : SSD_PLN_L */
  21         PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
  22         /* F12 : WWAN_RST_L */
  23         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  24         /* H3  : WLAN_PCIE_WAKE_ODL */
  25         PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
  26         /* H23 : WWAN_SAR_DETECT_ODL */
  27         PAD_CFG_GPO(GPP_H23, 1, DEEP),
  28
  29         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
  30         /* BT_I2S_BCLK */
  31         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
  32         /* BT_I2S_SYNC */
  33         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
  34         /* BT_I2S_SDO */
  35         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
  36         /* BT_I2S_SDI */
  37         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
  38         /* SSP2_SCLK */
  39         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
  40         /* SSP2_SFRM */
  41         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
  42         /* SSP_TXD */
  43         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
  44         /* SSP_RXD */
  45         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
  46 };
  47
  48 /* Early pad configuration in bootblock */
  49 static const struct pad_config early_gpio_table[] = {
  50         /* B4  : SSD_PERST_L */
  51         PAD_CFG_GPO(GPP_B4, 0, DEEP),
  52         /* F12 : GSXDOUT ==> WWAN_RST_L */
  53         PAD_CFG_GPO(GPP_F12, 0, DEEP),
  54         /* H12 : UART0_RTS# ==> SD_PERST_L */
  55         PAD_CFG_GPO(GPP_H12, 0, DEEP),
  56         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
  57         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  58         /* D6  : SRCCLKREQ1# ==> WWAN_EN */
  59         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  60         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
  61         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
  62         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  63         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  64         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
  65         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  66         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
  67         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  68         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
  69         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  70         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
  71         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  72         /* D11 : EN_PP3300_SSD */
  73         PAD_CFG_GPO(GPP_D11, 1, DEEP),
  74         /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
  75         PAD_CFG_GPO(GPP_H13, 1, DEEP),
  76 };
  77
  78 static const struct pad_config romstage_gpio_table[] = {
  79         /* B4  : SSD_PERST_L */
  80         PAD_CFG_GPO(GPP_B4, 1, DEEP),
  81
  82         /* Enable touchscreen, hold in reset */
  83         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
  84         PAD_CFG_GPO(GPP_C0, 1, DEEP),
  85         /* C1  : SMBDATA ==> USI_RST_L */
  86         PAD_CFG_GPO(GPP_C1, 0, DEEP),
  87
  88         /* H12 : UART0_RTS# ==> SD_PERST_L */
  89         PAD_CFG_GPO(GPP_H12, 1, DEEP),
  90 };
  91
  92 const struct pad_config *variant_gpio_override_table(size_t *num)
  93 {
  94         *num = ARRAY_SIZE(override_gpio_table);
  95         return override_gpio_table;
  96 }
  97
  98 const struct pad_config *variant_early_gpio_table(size_t *num)
  99 {
 100         *num = ARRAY_SIZE(early_gpio_table);
 101         return early_gpio_table;
 102 }
 103
 104 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 105 {
 106         *num = ARRAY_SIZE(romstage_gpio_table);
 107         return romstage_gpio_table;
 108 }